Material Loss Impact on Device Performance for 32nm CMOS and Beyond

Brian K. Kirkpatrick; James J. Chambers; Steven L. Prins; Deborah J. Riley; Wei Ze Xiong; Xin Wang

doi:10.4028/www.scientific.net/SSP.145-146.245

Paper Titles

Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process
p.227

Current Advances in Anhydrous HF/Organic Solvent Processing of Semiconductor Surfaces
p.231

Co-Solvent Effect on the HF/CO₂ Dry Etching of Sacrificial Oxides
p.235

A Novel Vapor Phase Etching Process for Si
p.239

Material Loss Impact on Device Performance for 32nm CMOS and Beyond
p.245

Evaluation of Plasma Strip Induced Substrate Damage
p.249

Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond
p.253

Influence of Dry Ashing and Wet Treatments on NVM Metal Gate Structures
p.257

Chemical and Mechanical Analysis of HDIS Residues Using Auger Electron Spectroscopy and Nanoindentation
p.261

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Material Loss Impact on Device Performance for 32nm CMOS and Beyond

Abstract:

As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.