Paper Titles

Contamination Control in Si ULSI-Technology at the 10¹¹cm^-3 - Level and below
p.109

Point Defect Engineering for ULSI Silicide Processing
p.121

Defect Control and Gettering in Cz-Silicon
p.137

Silicon Device Engineering by Intrinsic Point Defect Control
p.169

Defect Engineering in a High-Voltage Substrate Technology
p.175

Thermal Wafer Warpage and its Avoidance
p.181

Defects in Crystalline Silicon - History and Outlook
p.189

Defect Spectroscopy in Compound Semiconductors
p.195

Formation and Defect Structure of FeIn Pairs in Silicon
p.207

HomeSolid State PhenomenaSolid State Phenomena Vols. 19-20Defect Engineering in a High-Voltage Substrate...

Defect Engineering in a High-Voltage Substrate Technology

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Gettering and Defect Engineering in Semiconductor Technology IV

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Periodical:

Solid State Phenomena (Volumes 19-20)

Pages:

175-180

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.19-20.175

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Online since:

January 1991

Authors:

G. Kissinger, W. Kissinger, K. Tittelbach-Helmrich, U. Retzlaff, J. Knopke, K. Schmalz, G. Morgenstern

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© 1991 Trans Tech Publications Ltd. All Rights Reserved

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