Paper Titles

Defect Engineering in Submicron CMOS Technologies
p.95

Contamination Control in Si ULSI-Technology at the 10¹¹cm^-3 - Level and below
p.109

Point Defect Engineering for ULSI Silicide Processing
p.121

Defect Control and Gettering in Cz-Silicon
p.137

Silicon Device Engineering by Intrinsic Point Defect Control
p.169

Defect Engineering in a High-Voltage Substrate Technology
p.175

Thermal Wafer Warpage and its Avoidance
p.181

Defects in Crystalline Silicon - History and Outlook
p.189

Defect Spectroscopy in Compound Semiconductors
p.195

HomeSolid State PhenomenaSolid State Phenomena Vols. 19-20Silicon Device Engineering by Intrinsic Point...

Silicon Device Engineering by Intrinsic Point Defect Control

Article Preview

Abstract:

You might also be interested in these eBooks

Gettering and Defect Engineering in Semiconductor Technology IV

Info:

Periodical:

Solid State Phenomena (Volumes 19-20)

Pages:

169-174

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.19-20.169

Citation:

Cite this paper

Online since:

January 1991

Authors:

N.A. Sobolev, Yu.V. Vyzhigin, B.N. Gresserov, E.I. Sheck, A.I. Kurbakov, E.E. Rubinova, V.A. Trunov

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

© 1991 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation: