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Comparative Study of the Self-Aligned Channel Processes for 4H-SiC VDMOSFET
Abstract:
In this study, a novel self-aligned process is proposed to reduce the specific channel resistance, and the electrical characteristics affected by process variation are also verified through TCAD simulation. Also, when compared to other self-aligned processes, the process introduced in this paper offers the advantages of stable electrical characteristics and lower process costs.
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145-149
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August 2024
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