Comparative Study of the Self-Aligned Channel Processes for 4H-SiC VDMOSFET

Article Preview

Abstract:

In this study, a novel self-aligned process is proposed to reduce the specific channel resistance, and the electrical characteristics affected by process variation are also verified through TCAD simulation. Also, when compared to other self-aligned processes, the process introduced in this paper offers the advantages of stable electrical characteristics and lower process costs.

You might also be interested in these eBooks

Info:

Periodical:

Solid State Phenomena (Volume 359)

Pages:

145-149

Citation:

Online since:

August 2024

Export:

Share:

Citation:

* - Corresponding Author

[1] B. J. Baliga, Fundamentals of power semiconductor, second ed., Springer Cham, Berlin, (2019)

Google Scholar

[2] C. M. Zetterling, Process Technology for Silicon Carbide Devices, INSPEC, London, 2002.

Google Scholar

[3] W. Sung, K. Han and B. J. Baliga, A comparative study of channel designs for SiC MOSFETs: Accumulation mode channel vs. inversion mode channel, 29th International Symposium on Power Semiconductor Devices and IC's (2017), 375-378.

DOI: 10.23919/ispsd.2017.7988996

Google Scholar

[4] N. Miura et al., Jpn. J. Appl. Phys., 48, 04C085 (2009).

Google Scholar

[5] M. Matin, A. Saha, and J. A. Cooper, Jr., IEEE Trans. on Electron Devices, 51, 1721 (2004).

Google Scholar

[6] J. -Y. Jiang, T. -F. Chang and C. -F. Huang, , IEEE 11th International Conference on Power Electronics and Drive Systems, 678 (2015).

Google Scholar

[7] H. Runhua et al., J. Semiconductors, 36, 094002 (2015).

Google Scholar

[8] T. Morikawa, T. Ishigaki and A. Shima, IEEE Trans. on Electron Devices, 66, 3447 (2019).

Google Scholar