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Optimization of 1700V 4H-SiC JBS Diode Parameters

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Abstract:

The in-depth design optimization of the active layer of the 1700V class 4H-SiC JBS/MPS diode structure is discussed. The important design parameters such as junction depth (d), width (w) of p+ areas, and spacing (s) between them were optimized for the best possible trade-off between the unipolar ON-state voltage drop, the OFF-state breakdown voltage, and the bipolar surge current capability. The optimization was performed using a state-of-the-art simulator using device models calibrated on a commercially available JBS rectifier. The results show that the spacing s between the p+ regions is the most decisive parameter which has to be properly designed according to the required voltage class. For the 1700 V voltage class, s should be between 2 to 4 μm and the s/w ratio should be kept low. The depth d of the p+ pattern has a pronounced impact on the ignition of bipolar action such that with decreasing d the surge current capability decreases significantly.

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Periodical:

Materials Science Forum (Volume 858)

Pages:

782-785

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.858.782

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Online since:

May 2016

Authors:

Rupendra Kumar Sharma, Pavel Hazdra*, Stanislav Popelka, Andrei Mihaila, Holger Bartolf

Keywords:

Junction Barrier Schottky (JBS) Diode, Optimisation, Silicon Carbide (SiC), Surge-Current Moderation

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© 2016 Trans Tech Publications Ltd. All Rights Reserved

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