3D SOI Elements for System-on-Chip Applications

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Abstract:

Base technology of local 3D SOI-structures formation has been proposed. Using this technology the electrical characteristics were developed and simulated of following original device elements for the microsystem applications: standard and matrix SOI CMOS-transistors with 3D gates, switching elements on Schottky diodes, contact electrodes with 3D surface, elements for highly sensitive integral accelerometers with registration of a field emission current, hermetical microcavities and microchannels under the surface of a SOI-substrate, field emission silicon microcathodes.

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137-144

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July 2011

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© 2011 Trans Tech Publications Ltd. All Rights Reserved

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[1] Colinge J.P. Silicon-on-Insulator Technology: Materials to VLSI, 2nd Edition / Jean-Pierre Colinge. – NY: Kluwer Academic Publishers. – 1997. – 230 p.

Google Scholar

[2] Patent for the useful model № 36463 UA. Method of preparing the local three-dimensional structures the silicon-on-insulator. I.T. Kohut, V.I. Holota, A.O. Drushynin, S.V. Sapon Published 27. 10. 08, Bulletin № 20. 2008. – 14 p.

Google Scholar

[3] I.T. Kohut: Physics and chemistry of solid state Vol. 1 (2008), p.164.

Google Scholar

[4] I.T. Kohut et al.: bulletin of National University Lvivska Polytechnika Vol. 646 (2009), p.86.

Google Scholar

[5] Patent for the useful model № 29698 UA. Switching element on Schottky diodes with the structures silicon on the insulator. Kohut I.T., Holota V.I., Drushynin A.O. Published 25. 01. 2008, Bulletin № 2. 2008. – 10 p.

Google Scholar

[6] Patent for the useful model № 29701 UA. Contact in the integral devices with the structures silicon on the insulator. Kohut I.T., Drushynin A.O., Holota V.I. Published 25. 01. 2008, Bulletin № 2. 2008. – 10 p.

Google Scholar

[7] Patent for useful model № 43198 UA. Method of hermetic cavities formation in silicon wafer. I.T. Kohut, V.I. Holota Published 15. 08. 2008, Bulletin № 15. – 36 c.

Google Scholar

[8] Patent for useful model № 34277 UA. Method of local microstructures formation of type silicon-on-insulator,. Kohut I.T., Holota V.I., Dryshynin A.O., Sapon S.V. Published 11. 08. 2008. Bulletin № 15. – 10 c.

Google Scholar

[9] A. Druzhynin, V. Holota, I. Kohut, S. Sapon and Y. Khoverko: Electrochem. Soc. Trans., Vol 14 (2008), p.569.

DOI: 10.1149/1.2956075

Google Scholar