Investigating Dislocation Arrays Induced by Seed Scratches during PVT 4H-SiC Crystal Growth Using Synchrotron X-Ray Topography
p.71
p.71
Crystal Originated Defect Monitoring and Reduction in Production Grade SmartSiC™ Engineered Substrates
p.81
p.81
Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy Al Ions at Elevated Temperatures
p.87
p.87
Near-Interface Defect Decomposition during NO Annealing Analyzed by Molecular Dynamics Simulations
p.93
p.93
Differences between Polar-Face and Non-Polar Face 4H-SiC/SiO2 Interfaces Revealed by Magnetic Resonance Spectroscopy
p.99
p.99
Investigation of BPD Faulting under Extreme Carrier Injection in Room vs High Temperature Implanted 3.3kV SiC MOSFETs
p.105
p.105
Epitaxial Defectivity Characterization Combining Surface Voltage and Photoluminescence Mapping on 200mm 4H-SiC Wafers
p.111
p.111
Buffer Layer Dependence of Defectivity in 200mm 4H-SiC Homoepitaxy
p.117
p.117
A Study of Process Interruptions during Pre- and Post-Buffer Layer Epitaxial Growth for Defect Reduction in 4H SiC
p.123
p.123
Differences between Polar-Face and Non-Polar Face 4H-SiC/SiO2 Interfaces Revealed by Magnetic Resonance Spectroscopy
Abstract:
We performed electron-spin-resonance (ESR) and electrically-detected-magnetic-resonance (EDMR) spectroscopy on 4H-SiC(1120)/SiO2 interface defects to study differences between polar-face and non-polar-face 4H-SiC MOS interfaces. We found that in the non-polar-face MOS system, interface defects prefer to form spin-less states of doubly-occupied states and/or empty states, probably due to charge transfer between Si and C atoms at the interfaces.
You might also be interested in these eBooks
Info:
Periodical:
Defect and Diffusion Forum (Volume 434)
Pages:
99-103
Citation:
Online since:
August 2024
Authors:
Keywords:
Permissions:
Share:
Citation: