Device Performance and Reliability of SiC CMOS up to 400°C

Abstract:

This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

• Periodical: Key Engineering Materials (Volume 1024)
• Pages: 57-64
• DOI: https://doi.org/10.4028/p-rS5BUg
• Online since: September 2025
• Authors: Emran K. Ashik*, Sundar B. Isukapati, Hua Zhang, Tian Shi Liu, Utsav Gupta, Adam J. Morgan, Veena Misra, Woong Je Sung, Ayman Fayed, Anant K. Agarwal, Bong Mook Lee
• Keywords: BTI, Chemical Vapor Deposition, CMOS, Field Effect Mobility, Interface Traps, MOSFET, Reliability, Threshold Voltage, Transfer Characteristics

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