Key Engineering Materials Vol. 1024

Abstract: In addition to the well-known bias temperature instability (BTI) phenomena, recently, it has been revealed that SiC MOSFETs show another instability during high-frequency repetitive switching between VGS(L) and VGS(H), referred to as gate-switching instability (GSI). This study shows the increase in switching energy caused by gate-switching instability VGS(th) drift as key performance parameters in electric power conversion systems, especially, when operating in hard-switching mode. A new methodology based on double pulse test was applied at each readout. The results highlighted the significance of the degradation mechanism through its impact on hard-switching applications with high-switching frequency. Therefore ruggedness against GSI plays a pivotal role in the long-term reliable operation of SiC MOSFET devices to ensure durable and efficient power conversion systems.

Abstract: We identify one type of outlier SiC MOSFET device from massive parametric test that shows excessive channel leakage and abnormal subthreshold swing (S_S-TH) at low V_G (<1 V) and low I_D (<100 nA). Time-dependent dielectric breakdown (TDDB) and high temperature gate bias stress (HTGB) tests have been performed on these outlier devices to check their reliability. TDDB lifetime is shorter for a device with a higher S_S-TH, but there is no indication that the S_S-TH outliers would lead to an extrinsic failure. The post-PBTI I_D-V_G curve of the outlier device is overall shifted rightward and the off-state leakage at V_G=0 V is lower. The post-NBTI S_S-TH is reduced at I_D<100 nA and the off-state leakage is almost unchanged.

Abstract: This study demonstrates a negative correlation between gate leakage current () and time to breakdown () of gate oxide in various commercial SiC discrete MOSFETs and power modules. SiC MOSFETs with higher leakage current at the same gate voltage exhibit lower oxide failure time in the constant-voltage Time-Dependent Dielectric Breakdown (TDDB) test. The novelty lies in the discovery that measured under conditions of either low gate voltage () at RT or high at 150°C can be utilized to identify discrete devices or power modules with non-infant failures or lower intrinsic lifetime. Aggressive screening based on helps to reduce non-infant extrinsic failure probability and identify devices with more uniformity of intrinsic lifetime.

Abstract: In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the SiO₂/SiC MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density (~ 5×10¹⁰ eV^-1cm^-2), robust flat-band voltage stability under positive bias stress, and decent leakage current density (J_G ~ 5×10^-10 A cm^-2) can be unambiguously verified after nitric oxide (NO) gas post-deposition annealing.

Abstract: The aim of this study is to investigate the overcurrent turn-off robustness limit of SiC MOSFETs from three different manufacturers with three different cell technologies up to very high turn-off currents to determine a possible destruction limit and failure type. The influence of the negative gate-source voltage (V_GS,off) was studied because of the high drain-source overvoltage in connection with the decreased V_GS,off, which is the most critical point for the gate oxide field stress for the different cell technologies. All measurements were performed at a positive gate-source voltage (V_GS,on) above the specified datasheet values to reach high currents without channel pinch-off. In addition, the influence of temperature on the overcurrent robustness was studied. Finally, TCAD simulations were performed to determine the reason for the failure mechanism under the overcurrent turn-off conditions. All the manufacturer devices can withstand several times higher gate-source voltages under overcurrent conditions than the values recommended in the datasheet.

Abstract: VSC-HVDC systems are currently implemented in silicon IGBT technology. Advocates of SiC as a high voltage technology have long suggested that SiC has the potential to enhance the performance of VSC-HVDC systems by improving the energy conversion efficiency. The topology of choice for the latest VSC-HVDC systems is modular-multilevel-converters (MMC) comprised of cascaded half or full bridge sub-modules with voltages ranging between 1.3 kV and 2.8 kV. However, the current state of the art SiC power devices are still short of the ratings required for HVDC. Furthermore, the low switching frequencies used in MMC-VSC-HVDC means that conduction losses dominate hence, the fast-switching capability of SiC power devices is not necessarily an advantage. State of the art high voltage silicon IGBTs/PiN diodes exhibit comparable if not lower losses in comparison with commercially available SiC power MOSFETs/Schottky diodes of similar ratings. This review evaluates the potential performance of SiC power devices in MMC-VSC-HVDC systems, compares them with IGBT/IGCTs and reviews the challenges ahead for SiC devices.

Abstract: The improvement of the electrical properties of power semiconductors using engineered substrates is becoming increasingly significant. This paper investigates the dynamic performance and robustness of SiC MOSFETs based on SmartSiC^TM engineered substrates, focusing on the reverse recovery of the body diode and their ruggedness under overload conditions such as short-circuit and surge current. A comparison with SiC MOSFETs based on conventional monocrystalline substrates was performed to evaluate the results. A significant decrease in reverse recovery charge was observed, particularly at higher temperatures, while the robustness during short-circuit type I and surge current was not affected.

Abstract: This study evaluates the performance and reliability of SiC n-and p-MOSFETs across a temperature range from room temperature up to 400°C, focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below 3% and exhibit robust characteristics up to 400°C, p-MOSFETs exhibit permanent threshold voltage shifts of up to 10% and mobility reductions of 15% particularly above 300°C DC stress. The 2 nm ultrathin thermal (UT) followed by 40nm CVD SiO₂, outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to ±25V and temperatures as high as 400°C. This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Abstract: We are investigating 4H-SiC avalanche photodiodes for use as solar-blind, single-photon UV detectors, which could enable low cost, size, weight, and power devices that are reliable and robust, suitable for many sensing applications. One concern for these devices is the spatially-nonuniform gain which limits the useful device area and impedes the scaling necessary to compete with leading UV sensor architectures. We examined various potential sources of the nonuniformity, and conclude that the typically observed phenomenon is likely caused by impact ionization anisotropy and the 4° wafer offcut angle needed to maintain a consistent polytype during epitaxial growth. Additionally, we present both linear and Geiger-mode spatial maps on the same devices to explain the observed differences in each.