Preface
Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems
p.3
p.3
TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage
p.9
p.9
Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules
p.15
p.15
Achieving Low Dit (~5×1010eV-1cm-2), Competitive JG (~ 5×10-10 A cm-2) Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide
p.23
p.23
Investigation of Overcurrent Turn-Off Robustness of 1200 V SiC MOSFETs
p.29
p.29
Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications
p.39
p.39
Dynamic Characterization and Robustness of SiС MOSFETs Based on SmartSiCTM Engineered Substrates
p.49
p.49
Device Performance and Reliability of SiC CMOS up to 400°C
p.57
p.57
Achieving Low Dit (~5×1010eV-1cm-2), Competitive JG (~ 5×10-10 A cm-2) Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide
Abstract:
In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the SiO2/SiC MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density (~ 5×1010 eV-1cm-2), robust flat-band voltage stability under positive bias stress, and decent leakage current density (JG ~ 5×10-10 A cm-2) can be unambiguously verified after nitric oxide (NO) gas post-deposition annealing.
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Periodical:
Key Engineering Materials (Volume 1024)
Pages:
23-28
Citation:
Online since:
September 2025
Authors:
Umesh Chand*, Yu Chieh Chien, Abdul Hannan Yeo, Qin Gui Roth Voo, Shiv Kumar, Akhil Ranjan, Binni Varghese, Wei Jie Wang, Pavan Vudumula, Tamara Fidler, Patrick Schmid, Mario Saggio, Maurizio Castorina, Marco Camalleri, Jia Xie, Xiao Gong, Surasit Chung, Lakshmi Kanta Bera, Navab Singh, Yee Chia Yeo
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