TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Shuo Ben Hou; Christoffer Lundgren; Wlodek Kaplan; Sergey Reshanov

doi:10.4028/p-9eYPnN

Paper Titles

Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems
p.3

TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage
p.9

Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules
p.15

Achieving Low D_it (~5×10¹⁰eV^-1cm^-2), Competitive J_G (~ 5×10^-10 A cm^-2) Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide
p.23

Investigation of Overcurrent Turn-Off Robustness of 1200 V SiC MOSFETs
p.29

Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications
p.39

Dynamic Characterization and Robustness of SiС MOSFETs Based on SmartSiC^TM Engineered Substrates
p.49

Device Performance and Reliability of SiC CMOS up to 400°C
p.57

HomeKey Engineering MaterialsKey Engineering Materials Vol. 1024TDDB and HTGB Study of SiC MOSFET with Excessive...

TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Abstract:

We identify one type of outlier SiC MOSFET device from massive parametric test that shows excessive channel leakage and abnormal subthreshold swing (S_S-TH) at low V_G (<1 V) and low I_D (<100 nA). Time-dependent dielectric breakdown (TDDB) and high temperature gate bias stress (HTGB) tests have been performed on these outlier devices to check their reliability. TDDB lifetime is shorter for a device with a higher S_S-TH, but there is no indication that the S_S-THoutliers would lead to an extrinsic failure. The post-PBTI I_D-V_G curve of the outlier device is overall shifted rightward and the off-state leakage at V_G=0 V is lower. The post-NBTI S_S-THis reduced at I_D<100 nA and the off-state leakage is almost unchanged.