Strained Ge and Ge1-xSnx Technology for Future CMOS Devices

Abstract:

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We have investigated the growth and crystalline structures of Ge1-xSnx buffer and tensile-strained Ge layers for future use in CMOS technology. We have demonstrated that strain relaxed Ge1-xSnx layers with an Sn content of 12.3% and 9.2% can be grown on Ge and Si substrates, respectively. We achieved a tensile-strain value of 0.71 % in Ge layers on a Ge0.932Sn0.068 buffer layer. We have also investigated the effects of Sn incorporation into Ge on the electrical properties of Ge1-xSnx heteroepitaxial layers.

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Periodical:

Edited by:

Seiichi Miyazaki and Hitoshi Tabata

Pages:

146-151

DOI:

10.4028/www.scientific.net/KEM.470.146

Citation:

O. Nakatsuka et al., "Strained Ge and Ge1-xSnx Technology for Future CMOS Devices", Key Engineering Materials, Vol. 470, pp. 146-151, 2011

Online since:

February 2011

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Price:

$35.00

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