Impact of Device Design Parameters on 15 kV SiC MOSFETs

Abstract:

Experimental results from 15 kV-rated SiC DMOSFETs developed by GeneSiC Semiconductor are presented. A breakdown voltage of 16.7 kV is recorded, with < 200 nA leakage current at 15 kV. R_DS,ON in the range of 4-5 Ω, 12-15 Ω or 50-75 Ω were measured on MOSFETs with chip sizes of 25 mm², 16 mm² and 9 mm², respectively, with a lowest specific R_DS,ON of 238 mΩ-cm². The impact of MOSFET channel length and JFET width on the device performance is elucidated. Single-pulse avalanche energy = 22.1 J/cm² and t_AV=18.2 μs is achieved. V_G-+20 V gate stress applied at 175°C showed good V_TH stability with only a small 200-300 mV increase during the initial stages of the stress time.

• Periodical: Materials Science Forum (Volume 1062)
• Pages: 576-581
• DOI: https://doi.org/10.4028/p-1k1eb6
• Online since: May 2022
• Authors: Siddarth Sundaresan*, Jaehoon Park, Vamsi Mulpuri, Ranbir Singh
• Keywords: Device Design, On-Resistance, SiC-MOSFET, Ultra-High Voltage

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