Bias-Induced Instability of 4H-SiC CMOS

Abstract:

4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N₂-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

• Periodical: Materials Science Forum (Volume 1092)
• Pages: 103-107
• DOI: https://doi.org/10.4028/p-t5m16p
• Online since: June 2023
• Authors: Yu Xin Wen*, Bing Yue Tsui
• Keywords: Bias Temperature Instability (BTI), Post-Oxidation Annealing (POA), Silicon Carbide (SiC)

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