CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

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Abstract:

Electrochemical etching (ECE) of silicon carbide is a powerful route to porous 4H‑SiC. Yet, reliable pore initiation on the Si-face typically requires additional sophisticated pre-conditioning (e.g. masked KOH etching, metal-assisted photochemical etching (MAPCE), focused ion beam (FIB) milling), limiting industrial adoption. We demonstrate a simple, CMOS‑compatible pre‑conditioning based on short reactive‑ion‑etching (RIE) steps (10–30 s, SF₆/O₂) that reproducibly nucleate pores on the Si‑face of highly doped 4H‑SiC (resistivity < 0.02 Ω·cm) and enable homogeneous ECE in HF/ethanol without UV illumination. Surface roughness increases modestly with RIE time (Ra ≈ 1.3 nm to 4.0 nm), while subsequent ECE does not significantly degrade topography. SEM cross‑sections reveal continuous porous layers; image‑based quantification shows enhanced vertical pore alignment with longer RIE duration. A stepwise voltage program (11.5 V → 8.5 V → 11.5 V) yields stable current transients during etching. Eliminating noble metals and lithography reduces contamination risk. It improves process compatibility with front‑end manufacturing while remaining synergistic with our previously established ECE process flows and high‑temperature reorganisation of thin, porous SiC layers.

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