High-Purity Versus High-Defect-Density Semiinsulating Substrates for SiC MESFET: Simulation of Device Characteristics

Abstract:

Quantitative assessment of the influence of deep traps in semiinsulating (SI) SiC substrates on transient behavior and substrate leakage current of SiC MESFET is reported. Twodimensional device simulation confirmed that favorable reduction of the current-collapse happens when a fully depleted buffer is used. Simultaneously, the high-purity buffer causes an undesirable increase of the current bypassing the physical channel. A similar and even more pronounced effect is observed when very high purity SI substrates are used. The deep level-induced transient behavior disappears for the concentration of deep acceptor traps below the order of 1x1015 cm-3. However, this low trap concentration results in a virtual inability to pinch-off the channel even at very high gate biases. It has been demonstrated that the electric field preventing electron injection from thechannel into the substrate is very sensitive to the initial charge state of the traps prior to device biasing, which in turn is determined by the energy position of the deep levels in the substrate.

• Periodical: Materials Science Forum (Volumes 483-485)
• Pages: 869-872
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.483-485.869
• Online since: May 2005
• Authors: Yaroslav Koshka, Igor Sankin
• Keywords: Deep Level, MESFET, Semi-Insulating Substrate, Simulation, Surface States, Trapping

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