Effective Edge Termination Design in SiC VJFET

Article Preview

Abstract:

You might also be interested in these eBooks

Info:

Periodical:

Materials Science Forum (Volumes 483-485)

Pages:

877-880

Citation:

Online since:

May 2005

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2005 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] R.F. Davis, G. Kelner, M. Shur, et.al.: Proc. of the IEEE, Vol.79(1991), p.677

Google Scholar

[2] A.B. Horsfall, C.M. Johnson, et. al.: Mater. Sci. Forum Vol. 433-436(2003), p.777

Google Scholar

[3] P.Bhatnagar, A.B. Horsfall et al.: submitted to Solid State Electronics

Google Scholar

[4] D.C. Sheridian, et al.: Solid State Electronics 45(2001), p.1659

Google Scholar

[5] A.B. Horsfall, K.V. Vassilevski, et al.: Mater. Sci. Forum Vol. 389-393(2002), p.1149

Google Scholar

[6] Ranbir Singh, et al.: "High Temperature Characteristics of 5KV, 20A 4H-SiC PiN rectifiers", Proc. of ISPSD 2001, Osaka

Google Scholar

[7] A.S. Kyuregyan: Semiconductors, V. 34, Issue 7, p.835 (2000)

Google Scholar

[8] R.Rupp, et al.: "Performance and Reliability Issues of SiC-Schottky Diodes", Mater. Science Forum, Vol. 338-342(2000),p.1167 Current density vs Drain Volatge 0.00E+00 2.00E-03 4.00E-03 6.00E-03 8.00E-03 1.00E-02 1.20E-02 1.40E-02 1.60E-02 1.80E-02 0 500 1000 1500 Drain Voltage(V) Current Density(Acm -2 ) Device A with JTE Device B with JTE Device B no gate implant

DOI: 10.1158/1538-7445.sabcs15-ot2-02-03

Google Scholar