A New Generation of SiC Schottky Diodes with Improved Thermal Management and Reduced Capacitive Losses
With the help of an improved die attach the Rth,jc of SiC Schottky diodes can be reduced by 40-50% at a given chip size. This enables a significant higher power density for these SiC diode chips, resulting in a chip shrink of ~ 35% for a given nominal current. This has a significant impact not only on the cost position of the device but also on the switching performance of the diodes, as their capacitive charge directly scales with the chip area. Of course these advantages are accompanied by a small penalty in static losses as the Vf of the diodes at nominal current also slightly increases by the chip shrink. However, the reduction of switching losses dominates upon the marginally increased static losses besides full load operation conditions (which are pretty exceptional in today’s SiC Schottky diode applications) combined with frequencies below 130 kHz. This allows a better competitive positioning against fast Si-based diodes and improved system efficiency at the same time.
Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller
R. Rupp et al., "A New Generation of SiC Schottky Diodes with Improved Thermal Management and Reduced Capacitive Losses", Materials Science Forum, Vols. 645-648, pp. 885-888, 2010