Improved Observation of SiC/SiO2 Oxide Charge Traps Using MOS C-V
We have used C-V techniques to study the bias instability of 4H-SiC MOS capacitors and FETs, and compared those results to those obtained using ID-VGS. The net “back-and-forth” instability from C-V was found to exceed that of ID-VGS and matched closely with values from fast ID-VGS and midgap extrapolation, suggesting that the C-V method is more effective at measuring a “true” instability effect than ID-VGS alone. Using C-V, capacitors and large-area MOSFETs showed similar instability behavior, implying that the presence of minority carriers are not necessary to observe bias instability. One-way bias-stress C-V measurements reveal that most of the bias instability occurs under negative bias stress, whereas the opposite is observed in one-way bias stress ID-VGS measurements. Finally, post-oxidation NO annealing reduced the ΔVT bias instability for positive bias stress but does not appear to have influenced any of the other conditions.
Edouard V. Monakhov, Tamás Hornos and Bengt. G. Svensson
D. B. Habersat and A. J. Lelis, "Improved Observation of SiC/SiO2 Oxide Charge Traps Using MOS C-V", Materials Science Forum, Vols. 679-680, pp. 366-369, 2011