Materials Science Forum Vols. 717-720

Abstract: The sub-trenches in 4H-SiC Si- and C-faces could be disappeared by the thermal treatment in chlorine ambience at 900-1000oC. The surface morphologies of the thermally treated trench-sidewalls were unchanged. It is considered that the sub-trench is selectively removed because thermally Cl2 etching rate of the (0001) Si- and (000-1) C-face are different to the (11-20) and (1-100).

Abstract: 4H-SiC vertical bipolar power diodes have been fabricated with bilayer metallic anode contact based on an Al-Ti-Ni ohmic contact and a thick Al over-metallization. An optical window of 100 × 100 μm2 has been created through the anode contact with a SIMS Cameca IMS 4F equipment using Cs+ primary ions at 10 kV and with a beam spot size of 100 nm. The current/voltage characteristics of the diodes show that the SIMS process does not induce an increase of the leakage currents in forward nor in reverse bias. OBIC UV photogeneration occurs under the optical window and not under the contact metal.

Abstract: We report on experimental explorations of using focused ion beam (FIB) nanomachining of different types of silicon carbide (SiC) thin membranes, for making robust, high-quality stencil masks for new emerging options of nanoscale patterning. Using thin films and membranes in polycrystalline SiC (poly-SiC), 3C-SiC, and amorphous SiC (a-SiC) with thicknesses in the range of t~250nm−1.6μm, we have prototyped a series of stencil masks, with nanoscale features routinely down to ~100nm.

Abstract: We demonstrate a top-down fabrication technique for nanometer scale silicon carbide (SiC) pillars by using inductively coupled SF6/O2 plasma etching. The obtained SiC nanopillars exhibit high anisotropy features (aspect ratio ~ 6.5) with high etch depth (>7 μm). The etch characteristics of SiC nanopillars obtained under these conditions show a high etch rate (550 nm/min) and a high selectivity (over 60 for Ni mask). We obtained hexagonal symmetry of SiC nanopillar, which might be attributed to the crystallographic structure of the SiC phase.

Abstract: We have investigated 3C-SiC layers grown on silicon and on poli-Si in order to realize test MEMS structures. The strain of the films were investigated by the fabrication of cantilevers, beams, springs and we successfully fabricated a Double-Ended-Tuning-Fork double clamped SiC resonator on the film, with perfectly aligned actuation electrode.

Abstract: Anisotropic etching processes for mesa structure formation using fluorinated plasma atmospheres in an electron cyclotron resonance (ECR) plasma etcher were studied on Novasic substrates with 10 µm thick 3C-SiC(100) grown on Si(100). To achieve reasonable etching rates, a special gas inlet system suitable for injecting SF6 into the high density downstream Ar ECR plasma was designed. The influence of the etching mask material on the sidewall morphology was investigated. Masking materials with small grain sizes are preferable to achieve a desired shape. The evolution of the mesa form was investigated in dependence on the gas composition, the applied bias, the pressure and the composition of the gas atmosphere. The achieved sidewall slope was 84.5 deg. The aspect ratios of the fabricated structures in the developed residue free ECR plasma etching process were between 5 and 10. Mesa structures aligned to [100] and [110] directions were fabricated.

Abstract: In this work, local oxidation behavior in phosphorous ion-implanted 4H-SiC has been investigated by using atomic force microscopy (AFM). The AFM-local oxidation (LO) has been performed on the implanted samples, with and without activation anneal, using varying applied bias (15/20/25 V). It has been clearly shown that the post-implantation annealing process at 1650 oC has a great impact on the local oxidation rate by electrically activating the dopants and by modulating the surface roughness. In addition, the composition of resulting oxides changes depending on the doping level of SiC surfaces.

Abstract: The impact of threading dislocation density on the leakage current of reverse IV characteristics in 1.2 kV Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSDs), and PN junction diodes (PNDs) was investigated. The leakage current density and threading dislocation density have different positive correlations in each type of diode. For example, the correlation in SBDs is strong, but weak in PNDs. The threading dislocations were found to be in the same location as the current leakage points in the SBDs, but not in the PNDs. Nano-scale inverted cone pits were observed at the Schottky junction interface in SBDs, and it was found that leakage current increases in these diodes due to the concentration of electric fields at the peaks of the pits. These nano-scale pits were also observed directly above threading dislocations. In addition, this study succeeded in reducing the leakage current variation of 200 A-class JBSDs and SBDs by eliminating the nano-scale pits above the threading dislocations. As a result, a theoretical straight-line waveform was achieved.

Abstract: The 1200V class silicon carbide Schottky barrier diodes were designed and fabricated. The drift layer resistance was reduced in order to realize low forward voltage drops. Since the low drift layer resistance led to the low breakdown voltage, the avalanche withstanding capability should be enhanced not to cause the destructive breakdown. By means of the optimized device design, we succeeded to realize the low forward voltage drop while maintaining the high avalanche withstanding capability. The forward voltage drops at 200A/cm² were 1.35V at 25°C and 1.63V at 175°C, respectively. The avalanche withstanding capability was more than 3500mJ/cm² at 25°C. By substituting SiC-SBDs for Si-pin diodes, the estimated total power loss of the module comprised by Si-IGBTs and the diodes was reduced by 35%. We could also confirm that no failures happened after long term reliability tests.

Abstract: A significant performance gain of 650V SiC diodes is possible by reducing the wafer thickness from the standard thickness of 350 µm to < 150 µm. Not only the differential resistance of the diodes but also the Rth benefit from this chip thickness reduction. As consequence a further chip size reduction with accompanying capacitive charge reduction leads to a device with improved efficiency in PFC applications under both high load and low load conditions.