Materials Science Forum Vols. 717-720

Abstract: We investigate the passivation of interface traps by method of oxidizing Si-face 4H-SiC in the presence of potassium as well as examining the thermal stability of this passivation process. It is observed that this type of dry oxidation leads to a strong passivation of interface traps at the SiO2/4H-SiC interface with energy levels near the SiC conduction band edge. Furthermore, it is observed that if potassium ions residing at the SiO2/SiC interface are moved towards the sample surface by exposing them to ultraviolet light (UV) under an applied depletion bias stress at high temperatures the interface traps become electrically active again and are evidently depassivated. These findings are in line with recently a published model of the effect of sodium on such interface states

Abstract: The impact of ultraviolet (UV) light irradiation on thermally grown SiO₂/4H-SiC structures was investigated by characterizing the 4H-SiC metal-oxide-semiconductor (MOS) capacitors fabricated with and without UV irradiation onto the oxide layers. The UV irradiation was found to significantly increase a hysteresis in capacitance-voltage (C-V) characteristics and cause a positive flatband voltage (V_FB) shift, suggesting the generation of oxide charges and traps. Since the values of C-V hysteresis and V_FB shift depend on the UV irradiation time, the electrical defects were considered to be induced during UV irradiation. In contrast, UV irradiation caused no marked change for the reference Si-MOS capacitors, indicating that the generation of UV-induced electrical defects was an intrinsic property of thermally grown SiO₂/SiC structures. A detailed characterization of SiC-MOS capacitors with terraced SiO₂ layers revealed that the UV-induced defects were located near the SiO₂/SiC interface. The interfacial fixed charge density (Q_OX) was estimated to be 1.7×10¹² cm^-2 for the sample with UV irradiation, while that of the sample without UV irradiation was 1.0×10¹² cm^-2. Also, a slight increase was found in interface state density (D_it) due to UV irradiation. These results imply that the UV-induced defect generation correlates with residual carbon impurities at the SiO₂/SiC interface.

Abstract: The strong covalent bond of SiC imposes harsh post implantation annealing condition requirement for SiC MOS devices. As a consequence the effect of the annealing conditions on the channel region of the MOS devices becomes critical. High temperature microwave annealing has been shown to be an attractive alternative to conventional thermal annealing techniques. The effect of high temperature rapid microwave annealing on the performance of 4H-SiC MOS capacitors has been studied in this paper. Annealing temperatures ranging from 1600°C up to 2000°C for 30secs is used and the effect of annealing conditions is studied via C-V measurements on MOS capacitors.

Abstract: The recent development of silicon carbide complimentary metal-oxide-semiconductor (CMOS) is a key enabling step in the realisation of low power circuitry for high temperature applications, such as aerospace and well logging. This paper describes investigations into the properties of the gate dielectric as part of the development of the technology to realize monolithic fabrication of both n and p channel devices. A comparison of the oxide quality of the silicon carbide CMOS transistors is performed to examine the feasibility of this technology for high temperature circuitry.

Abstract: The SiC vacuum field-effect transistor (VacFET) was first reported in 2010 as a diagnostic tool for characterizing the fundamental properties of the inverted SiC semiconductor surface without confounding issues associated with thermal oxidation. In this paper, interface state densities are extracted from measurements of threshold voltage instability on a SiC VacFET and a SiC MOSFET. It is shown that removing the oxide can reduce the interface state density by more than 70%.

Abstract: Fabricated were 4H-SiC p-channel MOSFETs in two types of ion-implanted n-well regions and in the n-type substrate as a control. Effects of the n-well structure on the electrical properties were investigated. P-channel MOSFETs fabricated in the uniform doped n-well by using multiple ion-implantations showed inferior on-state characteristics to that of the control MOSFET, while those fabricated in the retrograde n-wells by using single-shot ion-implantation without additional implantation to form the surface p-type region indicated improved channel properties. The Vth values were controlled by the impurity concentration and depth of the surface p-type region, and the values of channel mobility were nearly equal to that of the control MOSFET. Good sub-threshold characteristics for the type II devices were demonstrated.

Abstract: The surface and interface roughness of SiO₂/4H-SiC(0001) was investigated in terms of Si emission from the interface and oxidation induced compressive stress. It was demonstrated that the SiO₂ surface roughness growth was strongly related with oxidation mechanism, as well as SiO₂ on Si substrate. A model for surface roughening was proposed with areal Si density and Young’s modulus to inclusively explain the surface roughness of SiO₂ on various substrates.

Abstract: The causes of extrinsic failures in time-dependent dielectric breakdown characteristics of gate oxide on C-face of 4H-SiC are examined by comparing breakdown points of tested gate oxides with the images of X-ray topography and those of differential interference contrast microscopy. We have concluded as follows: (1) surface morphological defects that originate from threading screw dislocations degrade reliability of gate oxides. (2) These surface defects are not necessarily found on every wafer. (3) Crystallographic defects are not killer defects of MOSFET per se.

Abstract: The quality of the SiC/SiO₂ interface is critical to the stability and performance of MOS-based SiC power devices. Charge pumping is a flexible interface characterization technique. In this work, a significant portion of the total traps are found to be located in the near-interface oxide using frequency-dependent charge pumping. Oxide trap tunneling mechanisms are discussed, and trap profile as a function of depth is calculated. The trap density is shown to increase exponentially as it gets closer to the interface.

Abstract: We describe fabrication of Van der Pauw (VDP) structures for characterization of gate oxides grown on 4H SiC epi surfaces. Implementation of sub-resolvable features (SRF) as a corner compensation mechanism is analyzed with challenges and advantages presented. Results of on-wafer screening tests suggest that implementation of SRFs widens tolerance for misalignment, producing similar yield between uncompensated VDPs with 0.2 micron overlap and compensated VDPs with 0.1 micron overlap for structures with best alignment. Optimization of SRFs for SiC could be an attractive option for extending lithographic capability in advanced devices.