Materials Science Forum Vols. 717-720

Abstract: Temperature dependent capacitance-voltage (C-V) and constant capacitance transient spectroscopy (CCDLTS) measurements have been performed to investigate the role of N in improving the transport properties of 4H-SiC MOS transistors. The higher channel mobility in the N pre-implanted transistors is due at least in part to activation of a small fraction of the implanted N near the SiO₂/SiC interface as donors in SiC during oxidation, thus reducing the effects of interface trapping. In addition, the absence of oxidation-induced near-interface defects, which were observed in NO-annealed capacitors, may contribute to the improved mobility in N pre-implanted transistors.

Abstract: The change in energy band alignment of thermally grown SiO2/4H-SiC(0001) structures due to an interface defect passivation treatment was investigated by means of synchrotron radiation photoelectron spectroscopy (SR-PES) and electrical characterization. Although both negative fixed charge and interface state density in SiO₂/SiC structures were effectively reduced by high-temparature hydrogen gas annealing (FGA), the conduction band offset (ΔE_c) at the SiO₂/SiC interface was found to be decreased by about 0.1 eV after FGA. In addition, a subsequent vacuum annealing to induce hydrogen desorption from the interface resulted in not only a slight degradation in interface property but also a partial recovery of ΔE_c value. These results indicate that the hydrogen passivation of negatively charged defects near the thermally grown SiO₂/SiC interface causes the reduction in conduction band offset. Therefore, the tradeoff between interface quality and conduction band offset for thermally grown SiO₂/SiC MOS structure needs to be considered for developing SiC MOS devices.

Abstract: A nitride layer was formed on a SiC surface by direct nitridation in pure N2 or in NH3 diluted with N2. The SiO2 layer was deposited by the thermal decomposition of tetraethylorthosilicate (TEOS) on the nitride layer to form an MIS diode. The XPS analysis showed that the nitride layer was oxidized during the deposition process of SiO2. The direct nitridation was effective to reduce the interface state density between the insulating layer and 4H-SiC

Abstract: The benefits of a new method used to incorporate nitrogen at the dielectric/semiconductor interface of 4H-SiC oxide-based devices are presented. High temperature exposure of the SiC surface to hydrogen and nitrogen, prior to oxide deposition, greatly reduces the amount of electrically active defects to a density at least as low as the one of thermally formed interfaces. These results demonstrate the potential of increasing minority carrier mobility with a low gate dielectric forming thermal budget, with deposited dielectrics, and with limited health hazards.

Abstract: In this article, we show some new results regarding the electrical properties of 4H-SiC MOSFETs fabricated by thermal annealing using POCl₃. The temperature dependence of MOSFET properties is described and the effect of POCl₃ annealing followed by forming gas annealing is shown. POCl₃-annealed MOSFETs indicates negative temperature dependence of channel mobility and smaller change in threshold voltage. Forming gas anneal after the POCl₃ treatment further improves channel mobility up to about 101 cm²/Vs. Features and problems of P-doped oxide are summarized and the future challenges are described.

Abstract: We have evaluated the reliability of POCl3-annealed oxides on 4H-SiC using time-zero dielectric breakdown (TZDB), constant current time-dependent dielectric breakdown (CC-TDDB), and high-frequency capacitance-voltage (C-V) measurements after electron injection. The POCl3 annealing does not deteriorate oxide breakdown field very much, still keeping an average value of larger than 9 MV/cm. However, the electron injection into POCl3-annealed oxide brings negative charges easily. From the C-V measurements, the POCl3-annealed capacitors were found to indicate a large positive flatband voltage shift after electron injection. Phosphorus atoms in the oxide may be related to the trapping site of injected electrons. The distribution and density of phosphorus in the oxide should be optimized to realize highly reliable 4H-SiC MOSFETs with high performance.

Abstract: Phosphorous passivation of the SiO2/4H-SiC interface lowers the interface trap density and increases the field effect mobility for n-channel MOSFETs to twice the value of 30-40cm2/V-s obtained using standard NO nitridation. Passivation using P2O5 introduced with an SiP2O7 planar diffusion source (PDS) converts the oxide layer to phosphosilicate glass (PSG) which is a polar material. BTS (bias‐temperature‐stress) measurements with MOS capacitors and FETs show that the benefits of reduced interface trap density and increased mobility are offset by unstable flat band and threshold voltages. This instability can be removed by etching away the PSG oxide and depositing a replacement SiO2 layer. However, trap densities for etched MOS capacitors are "NO-like" (i.e., higher), which would lead one to expect a lower mobility if MOSFETs are fabricated with the PSG / etch / deposited oxide process.

Abstract: This work provides data corroborating the presence of silicon oxycarbides (SiO_xC_y) in the SiO₂/SiC interface region. Besides, it presents results on the efficiency of hydrogen peroxide annealings for reducing the SiO₂/SiC interfacial region thickness. Finally, influences of water vapor thermal treatments on dielectric films thermally grown are presented. In most of the samples, isotopes rare in nature (¹⁸O and ²H) were used in thermal treatments associated with ion beam analyses.

Abstract: The effect of sequential thermal treatments with growth/removal steps of SiO₂ films intercalated with hydrogen peroxide treatments on the SiO₂/4H-SiC interfacial region thickness were investigated on both Si and C faces. In the Si face case, samples that were submitted to more H₂O₂ treatments presented thinner interfacial region thicknesses. In the C face case, on the other hand, no significant alteration in this region was observed.

Abstract: The electrical properties of the SiO₂/SiC interface fabricated by sodium-enhanced oxidation (SEO) of n-type 4H-SiC were studied by temperature-dependent C-V and constant-capacitance deep level transient spectroscopy (CCDLTS). With the exception of near-interface traps in the SiC epi-layer, which are not present in the SEO samples, the trap species observed in SEO capacitors are the same as those observed in both standard-oxidized and NO-annealed MOS capacitors. Total electron trapping in accumulation is comparable in SEO and NO-annealed capacitors; however, the traps in SEO capacitors are located at the interface whereas tunneling into oxide traps is observed in NO-annealed samples. A series of bias-temperature stress tests show that electron trapping is essentially unchanged when mobile sodium ions are moved toward the interface. The improved mobility attained by this process compared to NO annealing may be due to the absence of near-interface SiC traps in SEO samples.