Materials Science Forum Vols. 717-720

Abstract: We explore the effect of processing on graphene/metal ohmic contact resistance, the integration of high-κ dielectric seeds and overlayers on carrier transport in epitaxial graphene, and directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. We present a robust method for forming high quality ohmic contacts to graphene, which improves the contact resistance by nearly 6000x compared to untreated metal/graphene interfaces. Optimal specific contact resistance for treated Ti/Au contacts is found to average -7 Ohm-cm². Additionally, we introduce a novel seeding technique for depositing dielectrics by ALD that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Finally, we demonstrate that buffer elimination at the graphene/SiC(0001) results in excellent high frequency performance of graphene transistors with f_T > 130 GHz at 75 nm gate lengths.

Abstract: A bottom gate scheme is presented to tune the charge density of epitaxial graphene via a gate voltage while leaving the surface open for further manipulation or investigation. Depending on the doping concentration of the buried gate layer, the temperature and illumination, the bottom gate structure can be operated in two regimes with distinct capacitances. A model is proposed, which quantitatively describes the gate operation. The model is verified by a control experiment with an illuminated gate structure using UV light. Using UV illumination the Schottky capacitor (SC) regime, which provides improved gate efficiency, can be used even at low temperatures.

Abstract: To achieve graphene channel transistors which have high on/off drain current ratio and unipolar behavior of drain current – gate voltage (ID-VG) characteristics, we fabricated and characterized the top gated graphene channel transistors with n-type doped SiC source/drain regions. Graphene layer was formed on SiC by high temperature annealing in vacuum, and Al2O3 was used as a gate insulator. For the graphene channel transistor with heavily doped n-SiC source/drain regions (doping concentration ND=4.5x1019cm-3) and a 4~6ML graphene channel, ambipolar behavior was observed. On the other hand, when ND was reduced to 4.5x1018cm-3 and a thin graphene layer was used, the suppression of hole current in ID-VG curve was observed.

Abstract: Heteroepitaxial graphene on semiinsulating silicon carbide was used to fabricate nanoelectronic devices. T- and Y-branched graphene three-terminal junction devices were realized. Room temperature electrical measurements demonstrate pronounced nonlinear electrical properties of the devices. Voltage rectification at room temperature was observed. Increasing branch width reduces the curvature of the voltage rectification response curve of the three-terminal junc¬tions.

Abstract: Epitaxially grown single layer graphene on silicon carbide (SiC) resistive sensors were characterised for NO2 response at room and elevated temperatures, with an n-p type transition observed with increasing NO2 concentrations for all sensors. The concentration of NO2 required to cause this transition varied with different graphene samples and is attributed to varying degrees of substrate induced Fermi-level pinning above the Dirac point. The work function of a single layer device demonstrated a steady increase in work function with increasing NO2 concentration indicating no change in reaction mechanism in the concentration range measured despite a change in sensor response direction. Epitaxially grown graphene device preparation is challenging due to poor adhesion of the graphene layer to the substrate. A field effect transistor (FET) device is presented which does not require wire bonding to contacts on graphene.

Abstract: We investigated the chemical sensing mechanism of epitaxial graphene grown on 6H-SiC (0001) to different polar solvents and their behavior at higher temperatures. We show that at 300 K the sensitivity of the graphene sensor increases exponentially with the dipole moment of a solvent and decreases significantly as the temperature increased to 425 K. Using electrical measurements, we also show that graphene can effectively discriminate between polar protic and polar aprotic solvents with the shift in device electrical resistance at 300 K.

Abstract: The fundamental aspects of thermal oxidation and oxide interface grown on 4H-SiC(0001) Si-face and (000-1) C-face substrates were investigated by means of high-resolution x-ray photoelectron spectroscopy (XPS) using synchrotron radiation together with electrical measurements of SiC-MOS capacitors. We found that, for both cases, there existed no distinct C-rich transition layer despite the literature. In contrast, atomic scale roughness causing degradation of SiC-MOS devices, such as negative fixed charge and electrical defects just at the oxide interface, was found to be introduced as thermal oxidation progressed, especially for the (000-1) C-face substrate.

Abstract: Influences of wafer-related defect and gate oxide fabrication process on MOS characteristics with gate oxides thermally grown on 4H-SiC (0001) wafer have been investigated for a realization of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of DRY oxidation temperature and the applying of N2O and H2 POAs. In addition, it was clearly shown that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is effective technique for the improvement of SiC MOS reliability.

Abstract: We investigated the effect of post-oxidation annealing in wet O₂ and N₂O ambient, following dry O₂ oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO₂/SiC interface, in each POA process. Notably, the N₂O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O₂-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.

Abstract: Hall measurements on NO annealed 4H-SiC MOS gated Hall bars are reported in the temperature range 77 K- 423 K. The results indicate higher carrier concentration and lower trapping at increased temperatures, with a clear strong inversion regime at all temperatures. In stark contrast to Si, the Hall mobility increases with temperature for 77 K-373K, above which the mobility decreases slightly. The maximum experimental mobility was found to be ~50 cm² V^-1 s^-1 which is only about 10% of the 4H-SiC bulk mobility indicating that while NO annealing drastically improves trapping, it does not improve the mobility significantly. Supporting modeling results strongly suggest the presence of a disordered SiC channel region.