Materials Science Forum Vols. 717-720

Abstract: We experimentally investigated a method of controlling the energy barrier height (ΦB) of polycrystalline silicon (poly-Si)/4H-SiC heterojunction diodes (HJDs) and conducted a numerical simulation of a novel low Von and low reverse recovery current diode using ΦB control. The ΦB of the HJD with arsenic-doped n+-poly-Si was 0.79 eV and that of the HJD with boron-doped p+-poly-Si was 1.59 eV. The ΦB can be controlled over a wide range by varying the dopant and ion implantation dose of poly-Si. A novel merged HJD (M-HJD) with two different ΦB values obtained by using ΦB control is also presented. The numerical simulation results show that the M-HJD reduces Von without increasing reverse leakage current at high reverse voltage.

Abstract: Nitrogen-incorporated, n-type nanocrystalline diamond (NCD) films are deposited on p-type Si(001) and 4H-SiC(0001) substrates by moderate-pressure, microwave plasma-enhanced chemical vapor deposition using a mixture of 1%CH4-30%N2-69%Ar. X-ray diffraction and visible Raman spectroscopy reveal that the structure of the NCD films is identical independent of the substrate materials, such that diamond nanoparticles with apparent crystal sizes of 5-8 nm are embedded in amorphous sp² carbon matrix. For p-Si/n-NCD heterojunctions in a diode configuration, the rectifying behavior in current-voltage curves depends upon the substrate temperature for film deposition, and the rectification ratio reaches a maximum of about 300 when the film is deposited at 830 °C. For p-4H-SiC/n-NCD heterojunctions, the rectification ratio increases greatly to about 10000 when the film is deposited at 830 °C due exclusively to suppression of the reverse leakage current.

Abstract: Electron-hole recombination-induced stacking faults have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effects of bipolar injection induced stacking faults on the electrical characteristics of p+ ion-implanted high-voltage vertical-channel JFETs with 100-μm drift epilayers. The JFETs were stressed at a fixed gate-drain bipolar current density of 100 A/cm² for five hours, which led to degradation of the forward gate-drain p-n junction and on-state conduction. The degradation was fully reversed by annealing at 350 °C for 96 hours. Forward and reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Non-degraded characteristics remain unaffected by annealing events. Consequently, should minority carrier injection occur in JFETs operating at elevated temperatures no stacking fault induced degradations are expected. This eliminates the need for specialty substrates with suppressed densities of basal plane dislocations in the fabrication of high-voltage SiC JFETs for high temperature applications.

Abstract: This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

Abstract: A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in application. Normally-ON 1200 V SiC JFETs were stressed in hard-switching conditions to determine their fault handling capabilities. The hard-switching included single shot tests ranging from drain voltages of 100 V to 500 V and repetition rate tests at 1 Hz, 5 Hz, 10 Hz, and 100 Hz with peak currents exceeding 100 A (8 times the rated current at 250 W/cm²2). The JFET conduction and blocking-voltage characteristics are unchanged after 4,000 pulsed and numerous single shot hard switching events proving the devices are reliable for handling high surge-current faults.

Abstract: The energy dissipation capabilities of a 1200 V, 0.1 cm2 JFET operating in blocking mode were investigated. These devices, which are used in bidirectional circuit breaker applications, can conduct a current of 13 A in forward-conduction mode, and typically block a voltage up to 1200 V in blocking mode. In this document, the blocking limits of the device were pushed slightly to the point where avalanche breakdown occurs. A high voltage pulse generator was designed and constructed to drive the JFET into this state and to monitor the dissipated energy. The devices were able to handle up to 18.14 mJ.

Abstract: A high power discrete SiC-JFET package for accelerator applications has been developed and tested. Successful operation with a dc voltage of 1 kV, a drain current of 27 A, and a repetition rate of 1 MHz was confirmed. Thermal analysis was carefully attempted. The heat dissipation capacity of 235 W with a water-cooled heat sink and the thermal resistance from its junction to outer-surface of 0.56 K/W were demonstrated. These results exhibit the SiC-JFET is a promising device for a switching power supply in future digital accelerators.

Abstract: This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500°C silicon carbide (SiC) electronics and sensors, and test results of packaged SiC JFETs and capacitive pressure sensors at 500°C.

Abstract: We present the optimization of a standard lateral channel vertical JFET for high-frequency high-power applications. It will be shown that SiC JFETs are well suited to fulfill the requirements of certain RF applications when compared to silicon devices. Simulations covering the electrical characteristics will be given together with calculations considering the self-heating of the chip in pulsed-power applications and the corresponding decrease in saturation current. The gate-signal propagation will be analyzed for different chip layouts and the effect on switching speed will be described. Electrical results will demonstrate that the optimized JFET is suitable for RF-transmitter applications, like e.g. solid state RF modules as Klystron replacements in linear accelerators.

Abstract: In this paper, we describe the design of a high voltage SiC VJFET monolithically integrated with a JBS diode. The integrated device that was demonstrated up to 834 V in forward blocking doesn’t add any steps to the VJFET fabrication process. While the diode and VJFET share the same surface field termination mechanism, they are partially isolated using implanted field rings. We describe TCAD based optimization of the dimensions of these field rings and outline the design of the JBS diode using a fully analytical 2-D model.