Materials Science Forum Vols. 717-720

Abstract: In this work we present 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with a stable protective coating for harsh environment applications. Both inversion channel (IC) and buried channel (BC) MOSFETs were realized on n-4H-SiC substrates with a p-epilayer. Stacked ONO gate dielectric and Ti/TiN/Pt/Ti interconnect were used. Ni and Ti ohmic contacts in combination with a-SiOx/a-SiNy and a-SiOx/a-SiC protective coatings were compared. The MOSFETs showed excellent transistor characteristics up to 600 °C and exceptional stability during long-term aging at 600 °C in air and during accelerated aging at 700 °C including temperature cycling and air/moisture environment.

Abstract: Silicon Carbide VDMOS with integrated current and temperature sensors have been successfully fabricated without degradation of the chip forward or reverse characteristics due to the sensors. The temperature sensors show impedance correlated to the temperature, which permits to track the drift region’s temperature of the device. We have shown that the sensor current ratio can be influenced by the current spreading in the drift layer, especially when the channel resistance contribution is reduced. This aspect will be more critical on VDMOS with low channel resistance. Also, the sensor current ratio stability will be improved on devices with larger active area or thinner drift layer. Integration of such sensors will permit to monitor and protect innovative power electronic systems using SiC chips.

Abstract: High speed switching is desired to reduce switching losses of SiC-MOSFETs. In order to realize SiC-MOSFETs capable of high speed switching, we numerically evaluated the electric field induced in SiC-MOSFETs during switching using an equivalent circuit model. Based on the evaluation, we designed a SiC-MOSFET, which successfully demonstrated high speed switching with a dV/dt of over 70 V/ns.

Abstract: 4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering and velocity saturation.

Abstract: 4H-SiC MOSFETs with an epitaxial channel and NO postoxidation annealing have Si-like dependencies of noise on gate voltage. Such dependencies indicate that the density of the negatively charged oxide traps responsible for 1/f noise, N_tv, does not depend on the position of the Fermi level. The N_tv was found to be ~ 2×10¹⁹ cm^-3eV^-1. This value is considerably smaller than previously measured for transistors with ion implanted channels.

Abstract: Transistor performances of lateral and vertical 3C-SiC MOSFETs are investigated in the temperature range of 25 °C to 300 °C. Both types of MOSFETs operate up to 300 °C and the lateral MOSFETs possess peak channel mobility of more than 100 cm²/(Vs) even at 300 °C for the [110]- and [-110]-channel directions. In both MOSFETs, on-currents decrease monotonically and threshold voltages shift negatively as the temperature increases. The temperature dependence of on-currents in the lateral MOSFETs is weaker than that in the vertical MOSFETs. The leakage current at the negative gate voltage increases at above 200 °C. The activation energies calculated from the leakage currents at 200 °C and 300 °C are about half of the 3C-SiC bandgap energy of 2.3 eV.

Abstract: The channel mobility in 3C-SiC n-MOSFETs is investigated by current-voltage and Hall-effect measurements. For comparison, these techniques are also applied to 3C-SiC bulk rods. It turns out that the channel mobility depends on the orientation of the crystal and channel length. The observed results are traced back to the influence of Si-terminated stacking faults (Si-SFs), to the resistance of the drain/source contact and to the warping of the wafer caused by the special growth technique.

Abstract: We demonstrate 4H-SiC bipolar junction transistors (BJTs) with an enhanced current gain over 250. High current gain was achieved by utilizing optimized device geometry as well as optimized surface passivation, continuous epitaxial growth of the emitter-base junction, combined with an intentional deep-level-reduction process based on thermal oxidation to improve the lifetime in p-SiC base. We achieved a maximum current gain (β) of 257 at room temperature and 127 at 250°C for 4H-SiC BJTs fabricated on the (0001)Si-face. The gain of 257 is twice as large as the previous record gain. We also demonstrate BJTs on the (000-1)C-face that showed the highest β of 439 among the SiC BJTs ever reported.

Abstract: Large (4.3 mm2) area SiC BJTs were demonstrated with a current gain of 117 and a specific on-resistance of 2.8 mΩcm2. The open-base and open-emitter breakdown voltages are stable and with margin sufficient for 1200 V blocking. Fast and tail-current free switching behaviour was shown with rise- and fall-times in the range of 10-30 ns and the SiC BJTs were shown to be rugged in short-circuit and unclamped inductive switching.

Abstract: 1200 V-Class Super-High Current Gain Transistors or SJTs developed by GeneSiC are distinguished by low leakage currents of 2. Two-stage cascaded SJTs display a record high current gain of 3475. Results from detailed on-state, blocking, switching and reliability characterization of 1200 V-class 4 mm² and 16 mm² SiC SJTs are presented in this paper.