VF Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers

Chiharu Ota; Johji Nishio; Kazuto Takao; Takashi Shinohe

doi:10.4028/www.scientific.net/MSF.778-780.851

Paper Titles

Ultrahigh-Voltage (> 20 kV) SiC PiN Diodes with a Space-Modulated JTE and Lifetime Enhancement Process via Thermal Oxidation
p.832

Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC
p.836

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode
p.841

Development of SiC Super-Junction (SJ) Devices by Multi-Epitaxial Growth
p.845

V_F Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers
p.851

13-kV, 20-A 4H-SiC PiN Diodes for Power System Applications
p.855

Variant of Excess Current in 4H-SiC pn Structures
p.859

The Cryogenic Testing and Characterisation of SiC Diodes
p.863

Comparison of 5kV SiC JBS and PiN Diodes
p.867

HomeMaterials Science ForumMaterials Science Forum Vols. 778-780VF Degradation of 4H-SiC PiN Diodes Using Low-BPD...

V_F Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers

Abstract:

In this paper, we found origin of V_F degradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A V_F degradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered V_F degradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.