1200 V 4H-SiC DMOSFET with an Integrated Gate Buffer

Sei Hyung Ryu; Charlotte  Jonas; Craig Capell; Yemane Lemma; Anant Agarwal; Ty McNutt; Dave Grider; Scott T. Allen; John W. Palmour

doi:10.4028/www.scientific.net/MSF.778-780.939

Paper Titles

SiC Trench MOSFET with an Integrated Low Von Unipolar Heterojunction Diode
p.923

SiC Epi-Channel Lateral MOSFETs
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600 V -Class V-Groove SiC MOSFETs
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14.6 mΩcm² 3.3 kV DIMOSFET on 4H-SiC (000-1)
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1200 V 4H-SiC DMOSFET with an Integrated Gate Buffer
p.939

Designing of Quasi-Modulated Region in 4H-SiC Lateral RESURF MOSFETs
p.943

Utilization of SiC MOSFET Body Diode in Hard Switching Applications
p.947

Development of 3.3 kV SiC-MOSFET: Suppression of Forward Voltage Degradation of the Body Diode
p.951

High Temperature Reliability of the SiC-MOSFET with Copper Metallization
p.955

HomeMaterials Science ForumMaterials Science Forum Vols. 778-7801200 V 4H-SiC DMOSFET with an Integrated Gate...

1200 V 4H-SiC DMOSFET with an Integrated Gate Buffer

Abstract:

For the first time, a 1200 V 4H-SiC power MOSFET with a monolithically integrated gate buffer circuit has been demonstrated successfully. The device used a 6x10¹⁵ cm^-3 doped, 10 μm thick n-type drift layer to support 1200 V. The gate buffer circuit was built in a p-well, formed by boron ion implantation. The integrated device provided sufficient voltage isolation for the control circuit from the drain of the power MOSFET, and supported internal supply voltages up to 20 V. The operation of the integrated devices was demonstrated. A specific on-resistance (R_on,sp) of 20 mΩ-cm² was observed. The high R_on,sp was due to the limitations in NMOS pull-up circuit topology and the body effect in the 4H-SiC NMOSFET. Development of PMOS pull-up devices is recommended for future integration efforts.