Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications

Thi Thanh Huyen Nguyen; Mihai Lazar; Jean Louis Augé; Hervé Morel; Luong Viet Phung; Dominique Planson

doi:10.4028/www.scientific.net/MSF.858.982

Paper Titles

Improved Simulation Models for Designing Novel Edge Termination and Current Spreading Layers for 3300-V-Class 4H-SiC Implantation–Epitaxial MOSFETs with Low On-Resistance and Robustness
p.966

Silicon Carbide MOSFETs for Medium Voltage Megawatt Scale Systems
p.970

3.3 kV-Class 4H-SiC UMOSFET by Double-Trench with Tilt Angle Ion Implantation
p.974

Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices
p.978

Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications
p.982

High Performance of 5.7kV 4H-SiC JBSs with Optimized Non-Uniform Field Limiting Rings Termination
p.986

NO_x Sensing with SiC Field Effect Transistors
p.993

Exploring the Gas Sensing Performance of Catalytic Metal/Metal Oxide 4H-SiC Field Effect Transistors
p.997

Comparison of Bottom-Up and Top-Down 3C-SiC NWFETs
p.1001

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Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications

Abstract:

Recently, thanks to the advancement in SiC process technology, the deep trench termination (DT²) technique becomes an appropriate choice for future high voltage SiC power device. This technique termination is based on the use of a wide and deep trench, which is filled by a dielectric and associated with a field plate. DT² technique increases the breakdown voltage (V_BR) to a value near to the ideal one that can be obtained in a plan case; and at the same time, reduces drastically the chip area comparing to the previous conventional techniques. In this work, the DT² used for a 3 kV 4H-SiC bipolar vertical diode is presented. Simulations using TCAD SENTAURUS software show that a maximum breakdown voltage of 3286 V at room temperature can be achieved with a deep trench of 20μm corresponding to 98 % of a parallel plane breakdown voltage for the drift layer of 18 μm. Those simulations also point out the important impact of the structure of the trench; the dielectric critical electric filled (E_c), the permittivity (ε_r) of the dielectric filled, etching defects as microtrench, fixed charges at the interfaces...on the V_BR of power device.