Universal Parameter Evaluating SiO2/SiC Interface Quality Based on Scanning Nonlinear Dielectric Microscopy

Norimichi Chinone; Alpana Nayak; Ryoji Kosugi; Yasunori Tanaka; Shinsuke Harada; Yuji Kiuchi; Hajime Okumura; Yasuo Cho

doi:10.4028/www.scientific.net/MSF.897.159

Paper Titles

Improved Interface Trap Density Close to the Conduction Band Edge of a-Face 4H-SiC MOSFETs Revealed Using the Charge Pumping Technique
p.143

Conductance Signal from Near-Interface Traps in n-Type 4H-SiC MOS Capacitors under Strong Accumulation
p.147

Physical Characterisation of 3C-SiC(001)/SiO₂ Interface Using XPS
p.151

Functional Oxide as an Extreme High-k Dielectric towards 4H-SiC MOSFET Incorporation
p.155

Universal Parameter Evaluating SiO₂/SiC Interface Quality Based on Scanning Nonlinear Dielectric Microscopy
p.159

Electrical Properties and Interface Structure of SiC MOSFETs with Barium Interface Passivation
p.163

The Effect of Charge Redistribution on Flat-Band Voltage Turnaround in 4H-SiC MOS Capacitors
p.167

Three Dimensional Dislocation Analysis of Threading Mixed Dislocation Using Multi Directional Scanning Transmission Electron Microscopy
p.173

Correlation between Local Strain Distribution and Microstructure of Grinding-Induced Damage Layers in 4H-SiC(0001)
p.177

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Universal Parameter Evaluating SiO₂/SiC Interface Quality Based on Scanning Nonlinear Dielectric Microscopy

Abstract:

Oxidized both silicon-face (Si-face) and carbon-face (C-face) wafers with various post-oxidation-annealing conditions were measured by scanning nonlinear dielectric microscopy (SNDM) and method for evaluating SiO₂/SiC interface quality using SNDM was investigated. We found that the normalized standard deviation of SNDM image was good parameter to evaluate SiO₂/SiC interface of Si and C-face. SNDM measurement does not need electrode fabrication to measure C-V curve, but needs just scan on the oxidized wafer with conductive tip, which is easier and quicker. This technique enables us to quickly examine the effect of variation of process parameters in MOS fabrication and to effectively reduce the time needed for R&D cycle.