Improving Mechanical Strength and Surface Uniformity to Prepare High Quality Thinned 4H-SiC Epitaxial Wafer Using Si-Vapor Etching Technology

Satoshi Torimi; Koji Ashida; Norihito Yabuki; Masato Shinohara; Takuya Sakaguchi; Yoji Teramoto; Satoru Nogami; Makoto Kitabatake; Tadaaki Kaneko

doi:10.4028/www.scientific.net/MSF.897.375

Paper Titles

Enhanced Low-Temperature Oxidation of 4H-SiC Using SrTi_1-xMg_xO_3-δ
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Study of Etching Processes for SiC Defect Analysis
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Investigation on Wet Etching 4H-SiC Damaged by Ion Implantation
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4H-SiC Trench Structure Fabrication with Al₂O₃ Etching Mask
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Improving Mechanical Strength and Surface Uniformity to Prepare High Quality Thinned 4H-SiC Epitaxial Wafer Using Si-Vapor Etching Technology
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Fabrication of Thick Free-Standing Lightly-Doped n-Type 4H-SiC Wafers
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A Method to Adjust Polycrystalline Silicon Carbide Etching Rate Profile by Chlorine Trifluoride Gas
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Demonstrating the Instability of SiC Ohmic Contacts and Drain Terminal Metallization Schemes Aged at 300 °C
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Ni-Al-Ti Ohmic Contacts on Al Implanted 4H-SiC
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HomeMaterials Science ForumMaterials Science Forum Vol. 897Improving Mechanical Strength and Surface...

Improving Mechanical Strength and Surface Uniformity to Prepare High Quality Thinned 4H-SiC Epitaxial Wafer Using Si-Vapor Etching Technology

Abstract:

As a new thinning and surface planarizing process of Silicon Carbide (SiC) wafer, we propose the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. In this work, the effects of mechanical strength and surface step-terrace structure by Si-VE are investigated on the 4° off-axis 4H-SiC (0001) Si-face substrates. The indentation hardness of Si-VE surface is superior to the conventional chemo-mechanical polishing (CMP) surface even after epitaxial growth. The transverse strength of thinned Si-VE substrate is also superior to the conventional mechanically ground substrate. The surface step-terrace structures are observed by the low energy electron channeling contrast (LE-ECC) imaging technique. The latent scratch causes bunched step lines (BSLs) with various inhomogeneous step morphologies only on the CMP surface.

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Periodical:

Materials Science Forum (Volume 897)

Pages:

375-378

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.897.375

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Online since:

May 2017

Authors:

Satoshi Torimi*, Koji Ashida, Norihito Yabuki, Masato Shinohara, Takuya Sakaguchi, Yoji Teramoto, Satoru Nogami, Makoto Kitabatake, Tadaaki Kaneko

Keywords:

Latent Scratch, Low-Energy Electron Channeling Contrast Imaging (LE-ECCI), Mechanical Strength, Si-Vapor Etching, Stacking Fault, TaC, Thinned Wafer

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