Impact of Interface Trap Density of SiC-MOSFET in High-Temperature Environment

Shintaroh Sato; Masahiro Masunaga; Yuki Mori; Nobuyuki Sugii; Akio Shima

doi:10.4028/www.scientific.net/MSF.963.633

Paper Titles

1.2-kV SiC Trench-Etched Double-Diffused MOS (TED-MOS)
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An Investigation into the Dynamic Behavior of 3.3kV MOSFETs Body Diode
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Experimental Study of High-Temperature Switching Performance of 1.2kV SiC JBSFET in Comparison with 1.2kV SiC MOSFET
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Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits
p.629

Impact of Interface Trap Density of SiC-MOSFET in High-Temperature Environment
p.633

Performance Improvement of >10kV SiC IGBTs with Retrograde p-Well
p.639

Deep Trench Termination Structure with p-Type SiC Layer for Improved Reliability of High Voltage IGBT
p.643

Improved Device Characteristics Obtained Using a Novel High-K Dielectric Stack for 4H-SiC n-IGBT: HfO₂-SiO₂- AlN
p.647

15 kV n-GTOs in 4H-SiC
p.651

HomeMaterials Science ForumMaterials Science Forum Vol. 963Impact of Interface Trap Density of SiC-MOSFET in...

Impact of Interface Trap Density of SiC-MOSFET in High-Temperature Environment

Abstract:

We report the physical and electrical characterization of the inversion layer carrier and the shallow interface trap sites with n-and p-channel SiC-MOSFET in terms of high temperature electronics. This work proposes a physical model that explains the difference between I_d-V_g measurement result and calculation result supposing the ideal condition with Pao and Sah double ideal in room temperature. The measurement at 500°C confirmed our model so that inversion carrier were thermally excided, they could not be easily trapped by shallow trap sites, and I_d-V_g measurement result approached the ideal condition.

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Periodical:

Materials Science Forum (Volume 963)

Pages:

633-636

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.963.633

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Online since:

July 2019

Authors:

Shintaroh Sato*, Masahiro Masunaga, Yuki Mori, Nobuyuki Sugii, Akio Shima

Keywords:

Harsh Environment, High Temperature, Interface Trap Density, Inversion Layer, SiC-MOSFET, Threshold Voltage

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