Design of a 4H-SiC RESURF n-LDMOS Transistor for High Voltage Integrated Circuits

Abstract:

In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm² for a device with a RESURF structure with a total implanted Al concentration of 6∙10¹⁶ cm^-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

• Periodical: Materials Science Forum (Volume 963)
• Pages: 629-632
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.963.629
• Online since: July 2019
• Authors: Julietta Weisse*, Heinz Mitlehner, Lothar Frey, Tobias Erlbacher
• Keywords: 10 V-SiC-CMOS, Charge Compensation Devices, Integrated Circuit (IC), LDMOS, RESURF, Silicon Carbide

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