Avalanche Robustness of 4600 V SiC DMOSFETs

Siddarth G. Sundaresan; Vamsi Mulpuri; Stoyan  Jeliazkov; Ranbir Singh

doi:10.4028/www.scientific.net/MSF.963.777

Paper Titles

Influence of High-Temperature Bias Stress on Room-Temperature V_T Drift Measurements in SiC Power MOSFETs
p.757

Design Considerations for Robust Manufacturing and High Yield of 1.2 kV 4H-SiC VDMOS Transistors
p.763

Dynamic Characterization and Robustness Test of High Voltage SiC MOSFETs
p.768

Avalanche Ruggedness Characterization of 10 kV 4H-SiC MOSFETs
p.773

Avalanche Robustness of 4600 V SiC DMOSFETs
p.777

Reliability and Ruggedness of Planar Silicon Carbide MOSFETs
p.782

Capability of SiC MOSFETs under Short-Circuit Tests and Development of a Thermal Model by Finite Element Analysis
p.788

Comparative Study on the Repetitive Unclamped-Inductive-Switching Capability(R-UIS) of 1200V 160mOhm SiC Planar Gate MOSFETs
p.792

Superior Short Circuit Performance of 1.2kV SiC JBSFETs Compared to 1.2kV SiC MOSFETs
p.797

HomeMaterials Science ForumMaterials Science Forum Vol. 963Avalanche Robustness of 4600 V SiC DMOSFETs

Avalanche Robustness of 4600 V SiC DMOSFETs

Abstract:

A comprehensive investigation of the operating limits and failure modes for 4600 V/7.78 mm² SiC DMOSFETs under unclamped inductive switching (UIS) conditions is presented. Maximum single-pulse avalanche energies (E_AS) as high as 1.07 J (13.75 J/cm²) and avalanche withstand times (t_AV) as high as 71 μs are recorded. The variation of E_AS and t_AV with load inductance (or avalanche current) is quantified. Stability of the key DMOSFET performance characteristics including R_DS_,on, V_TH, body-diode, gate/drain leakage currents and terminal capacitances under both single-pulse and repetitive (up to 1000 shots) avalanche conditions are examined. Different failure locations confined within the active area of the DMOSFETs are identified after avalanche failure for either low or high E_AS failed devices and a tentative model to explain the failure physics is presented.