Influence of High-Temperature Bias Stress on Room-Temperature V_T Drift Measurements in SiC Power MOSFETs

Abstract:

Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (V_T) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for V_T stability.

• Periodical: Materials Science Forum (Volume 963)
• Pages: 757-762
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.963.757
• Online since: July 2019
• Authors: Daniel B. Habersat*, Aivars J. Lelis, Ronald Green
• Keywords: Bias Temperature Stress (BTS), High Temperature Gate Bias (HTGB), MOSFET, Qualification Standards, Silicon Carbide, Test Methods, Threshold Voltage

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