Via Cleaning Technology for Post Etch Residues
Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.
Paul Mertens, Marc Meuris and Marc Heyns
B.G. Sharma and C. Prindle, "Via Cleaning Technology for Post Etch Residues", Solid State Phenomena, Vols. 103-104, pp. 357-360, 2005