Via Cleaning Technology for Post Etch Residues

Abstract:

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Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

Info:

Periodical:

Solid State Phenomena (Volumes 103-104)

Edited by:

Paul Mertens, Marc Meuris and Marc Heyns

Pages:

357-360

DOI:

10.4028/www.scientific.net/SSP.103-104.357

Citation:

B.G. Sharma and C. Prindle, "Via Cleaning Technology for Post Etch Residues", Solid State Phenomena, Vols. 103-104, pp. 357-360, 2005

Online since:

April 2005

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Price:

$35.00

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