Solid State Phenomena Vols. 103-104

Abstract: We review the impact of semiconductor surface preparation on the performance of metal-oxidesemiconductor field-effect transistor (MOSFET) gate stacks. We discuss high-permittivity dielectrics such as hafnium oxide and aluminum oxide on silicon and on the high carrier mobility substrate germanium. On Si, scaling of the gate stack is the prime concern. On Ge, fundamental issues of chemical and electrical passivation need to be resolved. Surface treatments considered include oxidation, nitridation, hydrogenation, chlorination, and organic functionalization.

Abstract: High-k gate materials, such as HfO2, are unstable on silicon and form low permittivity interfacial oxides when heated. A single layer of silicon nitride grown prior to gate dielectric deposition could serve as a diffusion barrier to prevent oxide formation. A monolayer film of surface amine groups will be chemically similar to surface hydroxyl groups, and could also serve as a seed layer to promote the nucleation of a high-k film. The deposition of amines (≡Si-NH2 or ≡Si-NH-Si≡) on chlorine and hydrogen terminated Si(100) at low temperature (<100°C) was investigated using x-ray photoelectron spectroscopy (XPS). UV-Cl2 exposures (0.1-10 Torr Cl2 at 25-150°C, 10-600 s, 1000 W Xe lamp) were used to terminate Si(100) with Cl atoms. Exposure to NH3 (0.1-1000 Torr, 75°C, 5-60 min) replaced Cl atoms with up to 0.3 ML of amine groups, as measured by XPS. Cl atoms served as reactive leaving groups, lowering the overall activation energy barrier for nitridation. Alternatively, UV photons with energy greater than 5.7 eV were used to photodissociate NH3 molecules, yielding NH2 photofragments that reacted with the H-terminated Si(100) surface. At a UV photon flux of 19 mW/cm2, the N coverage increased with time and saturated at ~1 ML. Significant oxygen was observed on the surface due to H2O contamination in the source gas.

Abstract: This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.