Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement

Abstract:

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This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.

Info:

Periodical:

Solid State Phenomena (Volumes 103-104)

Edited by:

Paul Mertens, Marc Meuris and Marc Heyns

Pages:

37-40

DOI:

10.4028/www.scientific.net/SSP.103-104.37

Citation:

F. Arnaud et al., "Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement", Solid State Phenomena, Vols. 103-104, pp. 37-40, 2005

Online since:

April 2005

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Price:

$35.00

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