Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement

F. Arnaud; H. Bernard; Alessio Beverina; R. El-Farhane; B. Duriez; Kathy Barla; Didier Lévy

doi:10.4028/www.scientific.net/SSP.103-104.37

Paper Titles

On the Application of a Thin Ozone Based Wet Chemical Oxide as an Interface for ALD High-k Deposition
p.19

Interface State Densities and Surface Charge on Wet-Chemically Prepared Si(100) Surfaces
p.23

A Study of the Influence of Typical Wet Chemical Treatments on the Germanium Wafer Surface
p.27

Surface Preparation Techniques for High-k Deposition on Ge Substrates
p.31

Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement
p.37

Process, Environmental & Economical Considerations to Implement Single Wafer Cleaning Tools in 300mm Wafer Fabs
p.41

In Situ Wafer Processing for Next Generation Devices
p.45

Organic Contamination Control in Silicon Surface Processing
p.49

Application of UV/VIS-Spectroscopy for Determination of Complexing Agent Stability in APM and Like Mixtures Thereof
p.55

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Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement

Abstract:

This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.