Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow

Article Preview

Abstract:

As device features scale down to 90nm and Cu/low-k films are employed for back end interconnects, post etch and ash residue cleaning becomes increasingly challenging due to the higher aspect ratio of the features, tighter CD control requirements, sensitivity of the low-k films, and the requirement for high wet etch selectivity between CuxO and Cu. Traditional solvent based cleaning in wet benches has additional issues such as wafer cross-contamination and high disposal cost [1, 2]. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. The results of physical characterization, process integration electrical data, and process integration reliability data such as electromigration (EM) and stress migration data are presented. The main conclusions can be summarized as follows: (1) The single wafer cleaning process developed on the Oasis™ system can clean post etch residues and simultaneously clean the wafer front side and backside metallic contaminants; (2) In terms CuxO and Cu wet etch selectivity, CD loss control, the Oasis™ aqueous single wafer clean process is superior to the bench solvent cleaning process; (3)The Oasis aqueous cleaning process shows no undercut below etchstop due to the very low Cu etch amount in one cleaning pass, therefore the electromigration and stress migration performance of the aqueous Oasis processed wafers is clearly better than that of the solvent bench processed wafers.

You might also be interested in these eBooks

Info:

Periodical:

Solid State Phenomena (Volumes 103-104)

Pages:

353-356

Citation:

Online since:

April 2005

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2005 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] S. Loper, W. C. Ma and L. Chang: An Economical Solution for BEOL Post-ash Residue Removal, (Solid State Technology, June 2001).

Google Scholar

[2] R. Vroom, G. Gogg and J. O'Dwyer: BEOL Post ash Residue Removal Using DSP Chemistry in an FSI batch Spray Tool, (Trans Tech Publications, Switzerland, 2003).

DOI: 10.4028/www.scientific.net/ssp.92.117

Google Scholar

[3] M. R. Baklanov, T. Conard, F. Lankmans, et al., Characterization of Plasma Etch Related Residues Formed on Top of ECD Cu Films, (Advanced Metallization Conference 1999, MRS Proceedings, p.615~619.

Google Scholar

[4] U. Hong, S. Han, B. Park, et al. Influences of Cleaning Conditions and Elapse after Etch on Via Resistance in Multi-Level Cu Interconnects, Solid State Phenomena, Vol. 92 (2003), p.259~262.

DOI: 10.4028/www.scientific.net/ssp.92.259

Google Scholar

[5] L. Broussous, O. Hinsinger, S. Favier, P. Besson, Post Etch Cleaning Chemistries Evaluation for Low-k Cu Integration, Solid State Phenomena, Vol. 92 (2003), p.263~266.

DOI: 10.4028/www.scientific.net/ssp.92.263

Google Scholar

[6] A. Beverina, D. Louis, C. Arvet, et al., Post SiN Etching Cleaning During Copper and Low k Integration, Solid State Phenomena, Vols 76-77 (2001), p.101~104.

DOI: 10.4028/www.scientific.net/ssp.76-77.101

Google Scholar

[7] C. S. Hau-Riege and C. V. Thompson, Electromigration in Cu Interconnects with very DifferentGgrain Structures, Applied Physics Letters, volume 78, No. 22, May 2001.

DOI: 10.1063/1.1355304

Google Scholar

[8] J. Segura and C. Hawkins, CMOS Electronics, How It Works, How It fails, (Wiley Interscience, A John Wiley & Sons, INC., Publication). 2004. p.159~178.

DOI: 10.1002/0471728527

Google Scholar

[9] J. Tang, Lot 4348 Summary, Applied Materials Internal Research Report, June, 2004.

Google Scholar