Metal Hard Mask Employed Cu/Low k Film Post Ash and Wet Clean Process Optimization and Integration into 65nm Manufacturing Flow

Miao Chun Lin; Mei Qi Wang; Joe Lai; Ren Huang; Cheng Ming Weng; J.H. Liao; Jian She Tang; Ching Hwa Weng; Wei Lu; Han Wen Chen; John T.C. Lee

doi:10.4028/www.scientific.net/SSP.134.359

Paper Titles

Effect of Pressure Pulsation on Post-Etch Photoresist Stripping on Low-k Films in Supercritical CO₂
p.341

Optimization of a SC CO₂ Post-Etch Cleaning for Copper Interconnections
p.345

Study of Resist Strip Chemistries for Ultra Low-k/Cu Interconnect
p.351

Effect of Wafer Rotation on Photoresist Stripping in Supercritical CO₂
p.355

Metal Hard Mask Employed Cu/Low k Film Post Ash and Wet Clean Process Optimization and Integration into 65nm Manufacturing Flow
p.359

Mechanism and Principles of Post Etch Al Cleaning with Inorganic Acids
p.363

AlCu Metal Line Corrosion: A Case Study
p.367

Copper Surface Analysis with ToF-SIMS: Spectra Interpretation and Stability Issues
p.371

Influence of the Process Conditions of a Polishing Rinse after CuCMP
p.375

HomeSolid State PhenomenaSolid State Phenomena Vol. 134Metal Hard Mask Employed Cu/Low k Film Post Ash...

Metal Hard Mask Employed Cu/Low k Film Post Ash and Wet Clean Process Optimization and Integration into 65nm Manufacturing Flow

Abstract:

As 65nm technology in mass production and 45nm technology under development, post etch ash and cleaning faces new challenges with far more stringent requirements on surface cleanliness and materials loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. We have optimized a post etch ash process and developed a novel aqueous solution (AQ) based single wafer cleaning process to address these new defect modes. Physical characterization results and process integration electrical data are presented in this paper.

You might also be interested in these eBooks

Ultra Clean Processing of Semiconductor Surfaces VIII

View Preview

Info:

Periodical:

Solid State Phenomena (Volume 134)

Pages:

359-362

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.134.359

Citation:

Cite this paper

Online since:

November 2007

Authors:

Miao Chun Lin, Mei Qi Wang, Joe Lai, Ren Huang, Cheng Ming Weng, J.H. Liao, Jian She Tang, Ching Hwa Weng, Wei Lu, Han Wen Chen, John T.C. Lee

Keywords:

Cu/Low-k, Etch/Ash, Metal Hard Mask, Single Wafer Cleaning

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] C. Richard, et. al.; Barrier and seed layer wet etching, Solid State Phenomena, Vol. 103~104 (2005), p.361~364.

Google Scholar

[2] G. Delgadino, A. Zhao, et. al.; Tungsten hard mask damascene integration scheme for 65nm, 206th Meeting of the Electrochemical Society/2004 Fall Meeting of the Electrochemical Society of Japan, 2004, p.922.

Google Scholar

[3] Cheng Ming Weng, Miao Chun Lin, Ren Huang, US patent pending.

Google Scholar

[4] J. Segura and C. Hawkins, CMOS Electronics, How It Works, How It fails, (Wiley Interscience, A John Wiley & Sons, INC., Publication). 2004. p.159~178. (a) (b) 200nm 200nm (c) 200nm.

DOI: 10.1002/0471728527

Google Scholar