Wet Process Developments for Electrical Properties Improvement Of 3D MIM Capacitors

Abstract:

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3D architecture is an alternative way to high-k dielectric to increase the capacitance of MIM structure. However, the top of this kind of structure is very sensitive to defectivity and then requires a special wet treatment. In this paper, we present the process flow for a 3D MIM integration in a CMOS copper back-end and a two steps wet process which provides very good electrical performances, i.e. leakage current lower than 10-9A.cm-2 at 5V / 125°C and breakdown voltage higher than 20V. At first, a SC1 step is done for electrode isolation improvement by material etching with good selectivity towards dielectric: that’s the electrode recess. In the second time, a HF step is done for copper oxide dilution and residues removal from the top of the 3D structure.

Info:

Periodical:

Solid State Phenomena (Volume 134)

Edited by:

Paul Mertens, Marc Meuris and Marc Heyns

Pages:

379-382

DOI:

10.4028/www.scientific.net/SSP.134.379

Citation:

C. T. Richard et al., "Wet Process Developments for Electrical Properties Improvement Of 3D MIM Capacitors", Solid State Phenomena, Vol. 134, pp. 379-382, 2008

Online since:

November 2007

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Price:

$35.00

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