Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

Wen Dar Liu; Yi Chia Lee; Ryo Sekiguchi; Yukifumi Yoshida; Kana Komori; Kurt Wostyn; Farid Sebaai; Frank Holsteyns

doi:10.4028/www.scientific.net/SSP.282.101

Paper Titles

Electrostatic Discharge Control and Visualization in Spray Nozzle
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Behavior Analysis of Si Etching Process with HF/HNO₃ Mixture in Single-Spin Wafer Process
p.83

Study of the Anisotropic Wet Etching of Nanoscale Structures in Alkaline Solutions
p.88

Unexpected Pyramid Texturization of n-Type Ge (100) via Electrochemical Etching: Bridging Surface Chemistry and Morphology
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Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs
p.101

SiGe vs. Si Selective Wet Etching for Si Gate-all-Around
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A New Method to Fabricate Ge Nanowires: Selective Lateral Etching of Gesn:P/Ge Multi-Stacks
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Customized Chemical Compositions Adaptable for Cleaning Virtually all Post-Etch Residues
p.121

Low Temperature SiGe Steam Oxide - Aqueous Hf and NH₃/NF₃ Remote Plasma Etching and its Implementation as Si GAA Inner Spacer
p.126

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Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

Abstract:

A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.