Low Temperature SiGe Steam Oxide - Aqueous Hf and NH3/NF3 Remote Plasma Etching and its Implementation as Si GAA Inner Spacer

Kurt Wostyn; Karine Kenis; Hans Mertens; Adrian Vaisman Chasin; Andriy Hikavyy; Frank Holsteyns; Naoto Horiguchi

doi:10.4028/www.scientific.net/SSP.282.126

Paper Titles

Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs
p.101

SiGe vs. Si Selective Wet Etching for Si Gate-all-Around
p.107

A New Method to Fabricate Ge Nanowires: Selective Lateral Etching of Gesn:P/Ge Multi-Stacks
p.113

Customized Chemical Compositions Adaptable for Cleaning Virtually all Post-Etch Residues
p.121

Low Temperature SiGe Steam Oxide - Aqueous Hf and NH₃/NF₃ Remote Plasma Etching and its Implementation as Si GAA Inner Spacer
p.126

RMG Patterning by Digital Wet Etching of Polycrystalline Metal Films
p.132

Wet Etchants Penetration through Photoresist during Wet Patterning
p.141

Is Highly Selective Si₃N₄/SiO₂ Etching Feasible without Phosphoric Acid?
p.147

Self-Aligned Contacting Processes for the 80 nm p-MTJ Device Fabrication by Wet Approach
p.152

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Low Temperature SiGe Steam Oxide - Aqueous Hf and NH₃/NF₃ Remote Plasma Etching and its Implementation as Si GAA Inner Spacer

Abstract:

For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH₃/NF₃ remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si_0.75Ge_0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.