Yield Enhancement due to Addition of Bevel Cleans at Middle of Line(MOL) Zone

Article Preview

Abstract:

As the technology nodes become smaller and smaller the circuit dies get closer and closer to the edge of the wafer. Defects and issues on the bevel are seen to cause issues such as flaking and blocked plating on the dies at the edge of the wafer. This drastically increases the need for a clean wafer edge as the issues directly translate to yield loss at the end of the line. The wafer edge and backside are shown to have a significant impact on yield as well as process variation [1]. Introducing a dilute HF and SC1 bevel clean at the MOL layer resolves flaking and defect issues found on the bevel. Dispensing it on the backside of the wafer and ensuring that the chemistry is rolled over to the bevel results in the backside of the wafer becoming cleaner and helps resolve overlay issues. All the above stated effects are seen to result in an overall edge gain in edge yield.

You might also be interested in these eBooks

Info:

Periodical:

Solid State Phenomena (Volume 282)

Pages:

329-333

Citation:

Online since:

August 2018

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2018 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] Yield Enhancement White Paper,, International Roadmap for Devices and Systems 2016 Edition (2016).

Google Scholar

[2] Sherjang Singh et. al. Middle of Line (MOL) Cleaning Challenges in Sub-20nm Node Device Manufacturing,, UCPSS (2016).

DOI: 10.4028/www.scientific.net/ssp.255.105

Google Scholar

[3] Aaron Eppler, Controlling Uniformity At The Edge,, SEMICONDUCTOR ENGINEERING (2017).

Google Scholar

[4] KLA-TENCOR, Criticality Of Wafer Edge Inspection And Metrology Data To All-Surface Defectivity Root Cause And Yield Analysis,, SEMICONDUCTOR ENGINEERING (2018).

Google Scholar