Solid State Phenomena Vol. 376

Abstract: Indentation behavior induced by the presence of foreign inclusions in a PVT-grown 4H-SiC wafer is investigated through synchrotron X-ray topography, which revealed the generation of dislocation arrays from the inclusion center along six <11-20> directions. Grazing-incident topographs shows these dislocation arrays exhibit contrast configurations of opposite-signed TED pairs or BPD segments. This correlates with dislocation loops generated due to prismatic punching, and dislocation configuration variation is dependent on the position of prismatic loops with respect to the wafer surface. The stress induced by the inclusion embedded in the 4H-SiC matrix is estimated from the difference in the thermomechanical properties, as the crystal is cooled from the growth temperature.

Abstract: Several 1.2kV 4H-SiC devices of various cell architectures have been successfully fabricated by employing different P+ implantation conditions, resulting in varying levels of Basal Plane Dislocation (BPD) densities across the different device designs. It was found that by utilizing devices designed with an orthogonal P+ source layout as opposed to the traditional P+ stripe pattern, the long-term reliability under sustained 3rd Quadrant current stress conduction can be greatly improved even in devices with medium BPD densities. In addition, the use of the unipolar current of the JBSFET can further enhance long-term reliability under sustained 3^rd Quadrant current stress by mitigating stacking fault expansion, even in devices with a high BPD density.

Abstract: Electrical Wafer Sorting (EWS) on 12 000, 650 V SiC MOSFETs devices from 7 wafers of 200 mm 4H-SiC are compared with electrical deviations and defectivity of initial epitaxial layers measured using Charge biased non-Contact Voltage imaging, QUAD (Quality Uniformity And Defects), and optical surface detection with PL-imaging, respectively. We successfully demonstrate an increased prediction rate in both KR (kill-ratio) and YI (yield-impact) compared to conventional PL-imaging. It is also shown that QUAD not only supplements PL-imaging but supersedes it predicting failure in some electrical test conditions. We therefore show that the combination of QUAD and PL-imaging results significantly improves the accuracy of device failure prediction by uniquely locating faults in the wafers, and thus, improving foresight of successful device fabrication.

Abstract: In this paper, we have investigated the influence of growth-interruption during buffer layer growth on killer defect density in SiC epilayer grown over 4H-SiC (0001) substrates. We have observed that the growth-interruption method reduces total killer defect density by ~45(±5)%. Implementing growth-interruption in the buffer layer is a novel approach to mitigate epitaxial defects such as in-grown stacking faults (SFs), triangular defects, and basal plane dislocations (BPDs) in the drift layer and provide an extra margin to bipolar degradation by terminating BPDs early in the heavily doped buffer layer. The defect reduction mechanism in the presence of hydrogen has been simulated using Kinetic Monte Carlo (KMC) simulations.

Abstract: Bipolar degradation is a well-known issue when using body diodes in SiC-MOSFETs. Recent studies suggest that H⁺ (proton) implantation can effectively inhibit this degradation, but demonstrations on its suppression are still limited. Therefore, in this study, we have experimentally demonstrated how the expansion of Shockley-type stacking faults (SSFs) is suppressed by proton implantation. We fabricated a vertical SiC-MOSFET, in which protons were implanted into the middle depth of the drift layer. We then subjected the body diode to continuous current stress and performed photoluminescence (PL) analysis. Detailed PL image and emission spectral analysis of SSFs revealed that the proton-implanted layer can function as a recombination-enhancing layer during bipolar operation. Furthermore, it can be formed at any depth within the drift layer by controlling the energy, offering a significant advantage in the design of SiC-MOSFETs.

Abstract: Due to the lack of internationally accredited quality standards for silicon carbide (SiC) epiwafers, vendors provide defect maps using different metrology techniques and naming conventions, making it difficult to draw correlations between defect types and unclamped inductive switching (UIS) behavior. This study tested 1700 V rated Junction Barrier Schottky Diodes (JBS) using materials from five 4H-SiC epiwafer suppliers and concluded that, without maps having industry-standardized defect names and showing precise locations, sizes, and shapes, device manufacturers cannot effectively predict UIS yield and reliability.

Abstract: We introduce a polarization superimposed phase contrast microscope (PS-PCM) for wide-gap semiconductor wafers as a new analytical technique that enables non-destructive and three-dimensional characterization of threading dislocations; TSDs and TEDs in SiC epilayers and substrates, such as discrimination each other or detection of their inclination in the depth direction.

Abstract: We investigate the possibility to use silicon, titanium and tungsten as bonding materials between a SiC substrate and a SiC layer, a novel substrate for application in high-power electronics. By using transmission electron microscopy, scanning transmission electron microscopy and X-ray scattering techniques, we address the high temperature-induced phase and morphology changes in thin layers composed of these materials and at their interfaces with SiC. For all three materials, we show that the homogenous continuous film created after low temperature deposition transforms into a discontinuous structure following high temperature annealing. All layer’s structures tend to reach an epitaxial relation with the SiC substrates. In contrast to Si layer which preserves its composition, both Ti and W layers are transformed into new phases which were identified. We evidence that these peculiar structural and compositional changes in the layers, which were studied as a function of annealing temperature and time, are related to mechanisms of SiC dissolution and transport of C, Si, Ti, W atoms at the interface. Potential chemical and structural reactions during interface reconstructions are discussed in relation to the experimental findings.

Abstract: In this work we present the results of a comparison between the non-contact corona-based QUAD (Quality, Uniformity and Defects) technique for inline mapping of electrically active defects in SiC epi and final wafer level electrical device data on merged PiN Schottky diodes. A new defect analysis method for the QUAD mapping is introduced that involves the creation of a die yield bin map using the in-die values of depletion voltage that facilitates the comparison to the wafer level final electrical device data. Excellent correlation of the QUAD wafer bin map results to the final wafer level electrical device data was observed, illustrating that QUAD mapping of defects in SiC epi can provide a powerful and convenient inline complement to UVPL measurements for determining which defects are electrically active and will impact device performance.