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Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200mm SiC Wafers
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Dynamics of Stacking Fault Expansion in H⁺ Implanted SiC-MOSFETs
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HomeSolid State PhenomenaSolid State Phenomena Vol. 376Challenges in Investigating UIS Material-Based...

Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust 4H-SiС Epiwafer Quality Standards

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Abstract:

Due to the lack of internationally accredited quality standards for silicon carbide (SiC) epiwafers, vendors provide defect maps using different metrology techniques and naming conventions, making it difficult to draw correlations between defect types and unclamped inductive switching (UIS) behavior. This study tested 1700 V rated Junction Barrier Schottky Diodes (JBS) using materials from five 4H-SiC epiwafer suppliers and concluded that, without maps having industry-standardized defect names and showing precise locations, sizes, and shapes, device manufacturers cannot effectively predict UIS yield and reliability.

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Defects and Characteristics of SiC

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Periodical:

Solid State Phenomena (Volume 376)

Pages:

41-46

DOI:

https://doi.org/10.4028/p-QQ9CvK

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Online since:

September 2025

Authors:

Jake Soto*, Bruce Odekirk, Sergey Maximenko, Benjamin Rodgers, Matthew Fisher, Kevin Speer

Keywords:

Avalanche, Epitaxial Defects, JBS Diode, Photoluminescence, Quality Standards, Reliability, SiC, UIS, Unclamped Inductive Switching, UVPL, Yield

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Creative Commons CC BY 4.0

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* - Corresponding Author

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