Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Firas Faisal; Nils Steller; Robin Karhu; Birgit Kallinger; Gennadi Polisski; Marshall Wilson; Alexandre Savtchouk; Liliana Gutierrez; Carlos Almeida; Dmitriy Marinskiy; Jacek Lagowski

doi:10.4028/p-N8t06u

Paper Titles

Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 1.2kV 4H-SiC Power MOSFETs
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Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200mm SiC Wafers
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Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth
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Dynamics of Stacking Fault Expansion in H⁺ Implanted SiC-MOSFETs
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Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust 4H-SiС Epiwafer Quality Standards
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Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer
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High Temperature Evolution of Thin Films Confined between Two SiC Substrates
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Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data
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How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy
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HomeSolid State PhenomenaSolid State Phenomena Vol. 376Non-Contact Full Wafer Imaging of Electrically...

Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Abstract:

In this work we present the results of a comparison between the non-contact corona-based QUAD (Quality, Uniformity and Defects) technique for inline mapping of electrically active defects in SiC epi and final wafer level electrical device data on merged PiN Schottky diodes. A new defect analysis method for the QUAD mapping is introduced that involves the creation of a die yield bin map using the in-die values of depletion voltage that facilitates the comparison to the wafer level final electrical device data. Excellent correlation of the QUAD wafer bin map results to the final wafer level electrical device data was observed, illustrating that QUAD mapping of defects in SiC epi can provide a powerful and convenient inline complement to UVPL measurements for determining which defects are electrically active and will impact device performance.

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Periodical:

Solid State Phenomena (Volume 376)

Pages:

63-69

DOI:

https://doi.org/10.4028/p-N8t06u

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Online since:

September 2025

Authors:

Firas Faisal, Nils Steller, Robin Karhu, Birgit Kallinger, Gennadi Polisski, Marshall Wilson*, Alexandre Savtchouk, Liliana Gutierrez, Carlos Almeida, Dmitriy Marinskiy, Jacek Lagowski

Keywords:

CnCV, Defect, EOL Device, Epi, Non-Contact, QUAD, SiC

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Creative Commons CC BY 4.0

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* - Corresponding Author

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