Preface
Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers
p.1
p.1
Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 1.2kV 4H-SiC Power MOSFETs
p.11
p.11
Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200mm SiC Wafers
p.19
p.19
Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth
p.27
p.27
Dynamics of Stacking Fault Expansion in H+ Implanted SiC-MOSFETs
p.33
p.33
Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust 4H-SiŠ” Epiwafer Quality Standards
p.41
p.41
Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer
p.47
p.47
High Temperature Evolution of Thin Films Confined between Two SiC Substrates
p.55
p.55
Preface
Abstract:
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