Defect and Diffusion Forum Vol. 434

Abstract: We have investigated carbon behavior resulting from pressure control in furnace thermal oxidation process and evaluated the effect on gate oxide quality resulting from this pressure control. In order to investigate the potential reduction of carbon defects by reducing CO and CO₂, an analysis of oxidized SiC wafers was conducted. To evaluate the effect of pressure control related carbon component change during thermal oxidation, Q_BD characteristic was evaluated in SiC MOS Capacitance. The analysis results revealed on observable decrease in carbon at the SiO₂/SiC interface and the SiO₂ layer. The Q_BD results shown that improved at lower pressure better than those obtained in the general pressure.

Abstract: The influence of seed preparation on crystal defect generation is studied by investigating the effect of damage from surface scratches not completely removed during polishing on the seed crystal on the nucleation and evolution of dislocation arrays. Synchrotron X-ray topography is conducted on several wafers sliced from a PVT-grown 4H-SiC boule. Topographic results in conjunction with ray tracing simulation reveal the generation of TSD/TMD and TED arrays associated with the scratches in the newly grown wafer adjacent to the seed. Configuration transformation of those arrays is observed as these opposite-signed dislocation pairs composing the arrays were affected by the overgrowth of macro-steps when propagating into the newly grown crystal.

Abstract: Power devices electronics based on Silicon Carbide (SiC) are emerging as a breakthrough technology for various applications. The link between the quality of SiC substrates and device performance has been widely discussed [1]. Smart Cut™ technology offers the opportunity to integrate a high quality SiC layer on a low resistivity handle wafer. Moreover the crystal quality of a single donor wafer can be replicated multiple times to provide an epitaxy-ready substrate in high volume [2]. Nevertheless, some extended grown-in defects of SiC starting material, like micro-pipes or bulk inclusions, may generate surface defects called "Crystal Originated Defects" (COD) on transferred layers. This paper explains how SmartSiC™ defect density can be reduced by limiting the number of extended defects on donor wafers. Specific inspection recipes were developed to monitor the starting material and the replicated engineered substrate: COD root-causes and effects were analyzed. We demonstrated how a well-suited quality control of donor wafers plays a major role to guarantee defect-free SmartSiC™ wafers.

Abstract: 4H-SiC wafers with 12 µm epilayers were blanket implanted to a depth of 12 µm with 5 x 10¹⁶ cm^-3 Al ions via Tandem Van de Graaff accelerator located at Brookhaven National Laboratory with energy range of 13.8 to 65.7 MeV at room temperature, 300 °C and 600 °C. High resolution X-ray diffraction measurements reveal the implanted layers are characterized by tensile strains. However, the dynamic annealing process reduces the level of tensile strains as the temperature of implantation is increased. Analysis indicates that the implant temperature of 600 °C is not sufficient to minimize lattice damage due to implantation and a higher implantation temperature will be required. This preliminary experiment will guide the optimization of implantation conditions for fabricating superjunction devices.

Abstract: We have used molecular dynamics simulations to investigate the decomposition mechanisms of residual C defects near the interface of 4H-SiC/SiO₂ during NO annealing. We have observed drastically rapid defect decomposition by NO and O₂ mixed gas, which is thermodynamically more realistic, compared with single NO or O₂ gas annealing. We have constructed simplified defect decomposition model. This model numerically reproduced the simulation results, suggesting that multi-step and cooperative reactions caused by the coexistence of NO and O₂ during NO annealing effectively promote the decomposition of residual C defects.

Abstract: We performed electron-spin-resonance (ESR) and electrically-detected-magnetic-resonance (EDMR) spectroscopy on 4H-SiC(1120)/SiO₂ interface defects to study differences between polar-face and non-polar-face 4H-SiC MOS interfaces. We found that in the non-polar-face MOS system, interface defects prefer to form spin-less states of doubly-occupied states and/or empty states, probably due to charge transfer between Si and C atoms at the interfaces.

Abstract: Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x10¹⁸ cm^-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x10¹⁹ cm^-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

Abstract: Charge biased non-Contact Voltage imaging, QUAD (Quality Uniformity And Defects) is measured on epitaxial layers grown on 25 wafers of 200 [mm] 4H-SiC. Electrical data is analyzed and deviations in the ΔV signal are compared with defectivity observed by the optical surface detection system with UV-PL capability. Reliable statistical data of the relationship between decreasing voltage and defect classification show good detection of triangles and several other defects in the epitaxial layers. The QUAD mapping gives a good first indication of the electrical active defectivity of an epitaxial layer.

Abstract: The effect of increasing Buffer Layer (BL) thickness on crystal defectivity has been investigated in 4° off-axis 4H-SiC homoepitaxy on 200mm substrates coming from different suppliers. The results, based on optical microscopy and scatter light methods, show a slight increase in morphological defects in the case of a thicker BL with respect to the standard thickness for both suppliers.

Abstract: We perform epilayer growth where the process is interrupted (in situ) during post and pre buffer layer growth at a reduced temperature. Process interrupted during post buffer layer growth demonstrates significant reduction in basal plane dislocation (BPD) at a lower temperature. SIMS study demonstrates that etching takes place during the interruption time. We believe surface treatment of the buffer layer at different etching conditions during the interruption plays a major role in BPD reduction. However, the in-situ interruption, taking place prior to the buffer layer (i.e., on the substrate), does not contribute to the reduction in BPD in epilayer. We believe that the surface effect of interruption related etching on substrate during pre-buffer layer interruption, is not efficient enough to reduce BPD due to the higher doping and higher BPD associated with the substrate. Furthermore, we demonstrate that post buffer layer growth interruption contributes to the reduction in stacking faults in the epilayers. We also attribute this reduction of SF due to the surface etching prior to the drift layer growth.