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DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

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Abstract:

Local electrical properties of a 4H-Silicon Carbide SiC(0001) 4°off macrostepped surface, obtained after liquid Si melting in a SiC/Si/SiC sandwich configuration, are investigated by Atomic Force Microscopy (AFM) in both DC and RF modes. On the same sample, macrosteps that are wide enough for allowing spatial resolution of the signal from terraces and step risers, but also some unreacted areas with standard flat surface (without macrosteps) are characterized. Scanning Spreading Resistance (SSRM, DC mode) reveals homogeneous conductivity on the wide terraces of the 4H-SiC(0001) macrosteps. On unreacted areas, which contain many step risers, the resistance is found higher than on the wide terrasses but it is also noisier. In addition, the AFM-RF scanning Microwave Impedance Microscopy (sMIM) mapping confirms the previous results by revealing lower conductivity on the unreacted areas than on the terraces of the macrosteps. Based on these results, some points defects located at the step risers which contribute negatively to the electrical properties of 4H-SiC(0001) surface are identified and electrically characterized.

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Periodical:

Defect and Diffusion Forum (Volume 452)

Pages:

33-38

DOI:

https://doi.org/10.4028/p-epPB1m

Citation:

Cite this paper

Online since:

May 2026

Authors:

Rosine Coq Germanicus*, Gabriel Ferro

Keywords:

4H-SiC, AFM, Macrostepped Morphology, sMIM, SSRM, Surface Structuring

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Creative Commons CC BY 4.0

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References

[1] P. Fiorenza et al., "Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis," Nanotechnology, vol. 29, no. 39, p.395702, Jul. 2018.

DOI: 10.1088/1361-6528/aad129

Google Scholar

[2] J. Woerle et al., "Two-dimensional defect mapping of the SiO2/4H-SiC interface," Phys. Rev. Mater., vol. 3, no. 8, p.084602, Aug. 2019.

DOI: 10.1103/PhysRevMaterials.3.084602

Google Scholar

[3] M. Camarda, J. Woerle, V. Souliere, G. Ferro, H. Sigg, U. Grossner, and J. Gobrecht, Analysis of 4HSiC MOS Capacitors on macro-stepped surfaces, Mater. Sci. Forum, 897, (2017), 107–110.

DOI: 10.4028/www.scientific.net/MSF.897.107

Google Scholar

[4] N. Alyabyeva et al., "Nanoscale Mapping of Sub-Gap Electroluminescence from Step-Bunched, Oxidized 4H-SiC Surfaces," physica status solidi (b), vol. 260, no. 5, p.2200356, 2023.

DOI: 10.1002/pssb.202200356

Google Scholar

[5] Y. Jousseaume et al., "Controlled Macrostepping of Si-Face 4°off 4H-SiC over a Large Area via Liquid Si-Induced Reconstruction," Materials Science Forum, vol. 1089, p.9–14, 2023.

DOI: 10.4028/p-5p6o3j

Google Scholar

[6] Y. Jousseaume, P. Kumar, M. E. Bathen, F. Cauwet, U. Grossner, and G. Ferro, "Surface Structuring of Patterned 4H-SiC Surfaces Using a SiC/Si/SiC Sandwich Approach," Materials Science Forum, vol. 1124, p.7–12, 2024.

DOI: 10.4028/p-auZ0OI

Google Scholar

[7] P. Fiorenza et al., "Complementary Two Dimensional Carrier Profiles of 4H-SiC MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy," Solid State Phenomena, vol. 358, p.45–49, 2024.

DOI: 10.4028/p-9EfKbt

Google Scholar

[8] R. C. Germanicus, T. Phulpin, K. Niskanen, A. Michez, and U. Lüders, "AFM-sMIM Characterization of the Recombination-Enhancing Buffer Layer for Bipolar Degradation Free SiC MOSFETs," Solid State Phenomena, vol. 361, p.85–91, 2024.

DOI: 10.4028/p-hUPMo0

Google Scholar