Identification of High Resolution Transient Thermal Network Model for Power Module Packages
p.253
p.253
Transmission Electron Microscopy Study of Single Shockley Stacking Faults in 4H-SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on both Ends
p.258
p.258
Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology
p.263
p.263
Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method
p.268
p.268
Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation
p.273
p.273
Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection
p.278
p.278
Automatic Image Analysis of Stackingfault
p.283
p.283
Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures
p.288
p.288
Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis
p.293
p.293
Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation
Abstract:
We propose the new practical and effective method, called Selective E-V-C (Expansion-Visualization-Contraction) technique, to screen out the basal plane dislocations (BPDs) which might cause the forward voltage degradation of SiC devices. Since the method can be adopted at the epi wafer receiving inspection process in early stage of production line, it may replace the very time-consuming so-called "burn-in" operation currently utilized in some device manufacturers.
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Periodical:
Materials Science Forum (Volume 1062)
Pages:
273-277
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Online since:
May 2022
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